PIC24FJ128GA010-I/PT Microchip Technology, PIC24FJ128GA010-I/PT Datasheet - Page 41

• Manufacturer Part Number: PIC24FJ128GA010-I/PT
• Description: IC PIC MCU FLASH 128K 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ128GA010-I/PT

• Core Size: 16-Bit
• Program Memory Size: 128KB (43K x 24)
• Core Processor: PIC
• Speed: 16MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Controller Family/series: PIC24
• No. Of I/o's: 84
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• No. Of Pwm Channels: 5
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: SPI, I2C, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC24
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC164333 - MODULE SKT FOR PM3 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2MA160011 - DAUGHTER BOARD PICDEM LCD 16F91XDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

TABLE 3-27:
TABLE 3-28:
TABLE 3-29:
TABLE 3-30:
CRCCON
CRCXOR
CRCDAT
CRCWDAT
Legend:
RCON
OSCCON
CLKDIV
OSCTUN
Legend:
Note
NVMCON
NVMKEY
Legend:
Note
PMD1
PMD2
PMD3
Legend:
File Name
File Name
File Name
File Name
1:
2:
1:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
RCON register Reset values dependent on type of Reset.
OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset.
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Addr
Addr
Addr
Addr
0770
0772
0774
0640
0642
0644
0646
0740
0742
0744
0748
0760
0766
CRC REGISTER MAP
SYSTEM REGISTER MAP
NVM REGISTER MAP
PMD REGISTER MAP
TRAPR
Bit 15
Bit 15
Bit 15
T5MD
Bit 15
ROI
WR
—
—
—
—
—
—
IOPUWR
COSC2
Bit 14
T4MD
DOZE2
Bit 14
WREN
Bit 14
Bit 14
—
—
—
—
—
Bit 13
T3MD
COSC1
DOZE1
WRERR
Bit 13
Bit 13
CSIDL
Bit 13
—
—
—
—
—
IC5MD
Bit 12
T2MD
VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT
COSC0
DOZE0
Bit 12
Bit 12
—
Bit 12
—
—
—
—
IC4MD
Bit 11
T1MD
DOZEN
Bit 11
—
Bit 11
Bit 11
—
—
—
—
—
CMPMD
IC3MD
Bit 10
RCDIV2
NOSC2
—
Bit 10
Bit 10
Bit 10
—
—
—
—
RTCCMD
IC2MD
Bit 9
RCDIV1
NOSC1
—
Bit 9
CM
Bit 9
—
Bit 9
—
—
CRC XOR Polynomial Register
PMPMD
CRC Data Input Register
IC1MD
Bit 8
RCDIV0
VREGS
NOSC0
CRC Result Register
—
Bit 8
Bit 8
—
Bit 8
—
—
CRCPMD
I2C1MD
CLKLOCK
Bit 7
EXTR
—
Bit 7
Bit 7
Bit 7
—
—
—
U2MD
Bit 6
ERASE
Bit 6
SWR
—
—
Bit 6
Bit 6
—
—
—
SWDTEN
U1MD
Bit 5
LOCK
Bit 5
Bit 5
—
—
Bit 5
—
—
—
SPI2MD
OC5MD
CRCGO
WDTO
Bit 4
Bit 4
Bit 4
Bit 4
—
—
—
NVMKEY<7:0>
—
SPI1MD
OC4MD
SLEEP
NVMOP3 NVMOP2 NVMOP1 NVMOP0
PLEN3
Bit 3
Bit 3
Bit 3
CF
Bit 3
—
—
TUN<5:0>
OC3MD
PLEN2
Bit 2
Bit 2
IDLE
Bit 2
Bit 2
—
—
—
—
SOSCEN
OC2MD
I2C2MD
PLEN1
Bit 1
Bit 1
Bit 1
BOR
Bit 1
—
—
OSWEN
ADCMD
OC1MD
PLEN0
Bit 0
Bit 0
Bit 0
POR
Bit 0
—
—
Resets
Resets
Resets
Resets
xxxx
xxxx
0300
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
All
All
All
All
(1)
(2)
(1)