PIC24FJ128GA010-I/PT Microchip Technology, PIC24FJ128GA010-I/PT Datasheet
PIC24FJ128GA010-I/PT
Specifications of PIC24FJ128GA010-I/PT
Available stocks
Related parts for PIC24FJ128GA010-I/PT
PIC24FJ128GA010-I/PT Summary of contents
Page 1
... PIC24FJ128GA010 Family © 2009 Microchip Technology Inc. 64/80/100-Pin General Purpose, 16-Bit Flash Microcontrollers Data Sheet DS39747E ...
Page 2
... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
Page 3
... PIC24FJ96GA010 100 96K PIC24FJ128GA010 100 128K © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY Analog Features: • 10-Bit 16-Channel Analog-to-Digital Converter - 500 ksps conversion rate - Conversion available during Sleep and Idle • Dual Analog Comparators with Programmable Input/Output Configuration Peripheral Features: • ...
Page 4
... PIC24FJ128GA010 FAMILY Pin Diagrams 64-Pin TQFP PMD5/RE5 PMD6/RE6 PMD7/RE7 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/SS1/CN4/RB2 PGC1/EMUC1/V -/AN1/CN3/RB1 REF PGD1/EMUD1/PMA6/V +/AN0/CN2/RB0 REF DS39747E-page PIC24FJXXGA006 8 PIC24FJXXXGA006 SOSCO/T1CK/CN0/RC14 47 SOSCI/CN1/RC13 46 OC1/RD0 45 IC4/PMCS1/INT4/RD11 44 IC3/PMCS2/INT3/RD10 43 IC2/U1CTS/INT2/RD9 42 IC1/RTCC/INT1/RD8 41 Vss 40 OSC2/CLKO/RC15 39 OSC1/CLKI/RC12 ...
Page 5
... T2CK/RC1 4 T4CK/RC3 5 PMA5/SCK2/CN8/RG6 6 PMA4/SDI2/CN9/RG7 7 PMA3/SDO2/CN10/RG8 8 MCLR 9 PMA2/SS2/CN11/RG9 TMS/INT1/RE8 13 TDO/INT2/RE9 14 C1IN+/AN5/CN7/RB5 15 C1IN-/AN4/CN6/RB4 16 C2IN+/AN3/CN5/RB3 17 C2IN-/AN2/SS1/CN4/RB2 18 PGC1/EMUC1/AN1/CN3/RB1 19 PGD1/EMUD1/AN0/CN2/RB0 20 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY PIC24FJXXGA008 51 50 PIC24FJXXXGA008 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/RD11 IC3/PMCS2/RD10 IC2/RD9 IC1/RTCC/RD8 SDA2/INT4/RA15 SCL2/INT3/RA14 V SS OSC2/CLKO/RC15 OSC1/CLKI/RC12 V ...
Page 6
... PIC24FJ128GA010 FAMILY Pin Diagrams (Continued)) 100-Pin TQFP 1 RG15 PMD5/RE5 3 PMD6/RE6 4 PMD7/RE7 5 T2CK/RC1 6 T3CK/RC2 7 T4CK/RC3 8 T5CK/RC4 9 PMA5/SCK2/CN8/RG6 10 PMA4/SDI2/CN9/RG7 11 PMA3/SDO2/CN10/RG8 12 MCLR 13 PMA2/SS2/CN11/RG9 TMS/RA0 17 INT1/RE8 18 INT2/RE9 19 C1IN+/AN5/CN7/RB5 20 C1IN-/AN4/CN6/RB4 21 C2IN+/AN3/CN5/RB3 22 C2IN-/AN2/SS1/CN4/RB2 23 PGC1/EMUC1/AN1/CN3/RB1 24 PGD1/EMUD1/AN0/CN2/RB0 25 DS39747E-page PIC24FJXXGA010 63 PIC24FJXXXGA010 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/RD11 IC3/PMCS2/RD10 ...
Page 7
... Electrical Characteristics .......................................................................................................................................................... 211 27.0 Packaging Information.............................................................................................................................................................. 225 Appendix A: Revision History............................................................................................................................................................. 231 Index ................................................................................................................................................................................................. 233 The Microchip Web Site ..................................................................................................................................................................... 237 Customer Change Notification Service .............................................................................................................................................. 237 Customer Support .............................................................................................................................................................................. 237 Reader Response .............................................................................................................................................................................. 238 Product Identification System ............................................................................................................................................................ 239 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY DS39747E-page 7 ...
Page 8
... PIC24FJ128GA010 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. ...
Page 9
... OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC24FJ128GA010 family offer five different oscillator options, allowing users a range of choices in developing application hardware. These include: • Two Crystal modes using crystals or ceramic resonators. ...
Page 10
... DS39747E-page 10 1.3 Details on Individual Family Members Devices in the PIC24FJ128GA010 family are available in 64-pin, 80-pin and 100-pin packages. The general block diagram for all devices is shown in Figure 1-1. The devices are differentiated from each other in two ways: 1. ...
Page 11
... TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ128GA010 FAMILY Features Operating Frequency Program Memory (Bytes) 64K Program Memory (Instructions) 22,016 Data Memory (Bytes) Interrupt Sources (Soft Vectors/NMI Traps) I/O Ports Ports Total I/O Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) ...
Page 12
... PIC24FJ128GA010 FAMILY FIGURE 1-1: PIC24FJ128GA010 FAMILY GENERAL BLOCK DIAGRAM Interrupt Controller PSV & Table Data Access Control Block 23 23 Address Latch Program Memory Data Latch Address Bus Instruction Decode & Control Power-up Timing OSC2/CLKO Timer Generation OSC1/CLKI Oscillator Start-up Timer FRC/LPRC ...
Page 13
... TABLE 1-2: PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS Pin Number Function 64-Pin 80-Pin AN0 16 20 AN1 15 19 AN2 14 18 AN3 13 17 AN4 12 16 AN5 11 15 AN6 17 21 AN7 18 22 AN8 21 27 AN9 22 28 AN10 23 29 AN11 24 30 AN12 27 33 AN13 28 34 AN14 29 35 ...
Page 14
... PIC24FJ128GA010 FAMILY TABLE 1-2: PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin 80-Pin 100-Pin CN18 32 40 CN19 — 65 CN20 — 37 CN21 — REF EMUC1 15 19 EMUD1 16 20 EMUC2 17 21 EMUD2 18 22 ENVREG 57 71 IC1 42 54 IC2 43 55 IC3 44 56 IC4 ...
Page 15
... TABLE 1-2: PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin 80-Pin PMA0 30 36 PMA1 29 35 PMA2 8 10 PMA3 6 8 PMA4 5 7 PMA5 4 6 PMA6 16 24 PMA7 22 23 PMA8 32 40 PMA9 31 39 PMA10 28 34 PMA11 27 33 PMA12 24 30 PMA13 23 29 PMBE ...
Page 16
... PIC24FJ128GA010 FAMILY TABLE 1-2: PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin 80-Pin 100-Pin RA0 — — RA1 — — RA2 — — RA3 — — RA4 — — RA5 — — RA6 — — RA7 — — RA9 — ...
Page 17
... TABLE 1-2: PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin 80-Pin RD0 46 58 RD1 49 61 RD2 50 62 RD3 51 63 RD4 52 66 RD5 53 67 RD6 54 68 RD7 55 69 RD8 42 54 RD9 43 55 RD10 44 56 RD11 45 57 RD12 — 64 RD13 — 65 RD14 — ...
Page 18
... PIC24FJ128GA010 FAMILY TABLE 1-2: PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin 80-Pin 100-Pin RG0 — 75 RG1 — 74 RG2 37 47 RG3 36 46 RG6 4 6 RG7 5 7 RG8 6 8 RG9 8 10 RG12 — — RG13 — — RG14 — — RG15 — ...
Page 19
... TABLE 1-2: PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin 80-Pin U1CTS 43 37 U1RTS 35 38 U1RX 34 42 U1TX 33 41 U2CTS 21 27 U2RTS 29 35 U2RX 31 39 U2TX 10, 26, 38 12, 32 16, 37 DDCAP DDCORE REF REF V 9, 25, 41 11, 31, 51 15, 36, 45, SS Legend: TTL = TTL input buffer ANA = Analog level input/output © ...
Page 20
... PIC24FJ128GA010 FAMILY NOTES: DS39747E-page 20 © 2009 Microchip Technology Inc. ...
Page 21
... Instructions are associated with predefined addressing modes depending upon their functional requirements. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY For most instructions, the core is capable of executing a data (or program data) memory read, a working reg- ister (data) read, a data memory write and a program (instruction) memory read per instruction cycle ...
Page 22
... PIC24FJ128GA010 FAMILY FIGURE 2-1: PIC24F CPU CORE BLOCK DIAGRAM PSV & Table Data Access Control Block Interrupt Controller 8 23 PCH 23 Program Counter Stack Control Logic 23 Address Latch Program Memory Address Bus Data Latch 24 Instruction Decode & Control Control Signals to Various Blocks ...
Page 23
... W12 W13 W14 W15 22 Registers or bits shadowed for PUSH.S and POP.S instructions. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY Description Working Register Array 23-Bit Program Counter ALU STATUS Register Stack Pointer Limit Value Register Table Memory Page Address Register Program Space Visibility Page Address Register ...
Page 24
... PIC24FJ128GA010 FAMILY 2.2 CPU Control Registers REGISTER 2-1: SR: CPU STATUS REGISTER U-0 U-0 U-0 — — — bit 15 (1) (1) R/W-0 R/W-0 R/W-0 (2) (2) IPL2 IPL1 IPL0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-9 Unimplemented: Read as ‘0’ ...
Page 25
... PSV: Program Space Visibility in Data Space Enable bit 1 = Program space visible in data space 0 = Program space not visible in data space bit 1-0 Unimplemented: Read as ‘0’ Note 1: User interrupts are disabled when IPL3 = 1. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY U-0 U-0 U-0 — — — U-0 ...
Page 26
... PIC24FJ128GA010 FAMILY 2.3 Arithmetic Logic Unit (ALU) The PIC24F ALU is 16 bits wide and is capable of addi- tion, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, the ALU may affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register ...
Page 27
... The program address memory PIC24FJ128GA010 family devices is 4M instructions. The space is addressable by a 24-bit value derived from FIGURE 3-1: PROGRAM SPACE MEMORY MAP FOR PIC24FJ128GA010 FAMILY DEVICES PIC24FJ64GA GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table User Flash ...
Page 28
... On device Reset, the config- uration information is copied into the appropriate Configuration registers. The addresses of the Flash Configuration PIC24FJ128GA010 family are shown in Table 3-1. Their location in the memory map is shown with the other memory vectors in Figure 3-1. The Configuration Words in program memory are a compact format ...
Page 29
... All Effective Addresses (EAs) in the data memory space are 16 bits wide, and point to bytes within the data space. This gives a data space address range of 64 Kbytes, or 32K words. The lower half of the data FIGURE 3-3: DATA SPACE MEMORY MAP FOR PIC24FJ128GA010 FAMILY DEVICES MSB Address 0001h 07FFh ...
Page 30
... PIC24FJ128GA010 FAMILY 3.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT To maintain backward compatibility with PIC and improve data space memory usage efficiency, the PIC24F instruction set supports both word and byte operations consequence of byte accessibility, all effective address calculations are internally scaled to step through word-aligned memory. For example, the ...
Page 31
TABLE 3-3: CPU CORE REGISTERS MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 ...
Page 32
TABLE 3-4: INTERRUPT CONTROLLER REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 INTCON1 0080 NSTDIS — — — INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — AD1IF U1TXIF IFS1 0086 U2TXIF U2RXIF INT2IF ...
Page 33
TABLE 3-5: ICN REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CNEN2 0062 — — — — CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE ...
Page 34
TABLE 3-7: INPUT CAPTURE REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 IC1BUF 0140 IC1CON 0142 — — ICSIDL — IC2BUF 0144 IC2CON 0146 — — ICSIDL — IC3BUF 0148 IC3CON 014A — — ICSIDL ...
Page 35
TABLE 3-9: I2C1 REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 I2C1RCV 0200 — — — — I2C1TRN 0202 — — — — I2C1BRG 0204 — — — — I2C1CON 0206 I2CEN — I2CSIDL SCLREL ...
Page 36
TABLE 3-11: UART1 REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 U1MODE 0220 UARTEN — USIDL IREN U1STA 0222 UTXISEL1 TXINV UTXISEL0 — U1TXREG 0224 — — — — U1RXREG 0226 — — — — ...
Page 37
TABLE 3-15: ADC REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ADC1BUFB 0316 ...
Page 38
TABLE 3-17: PORTB REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 (1) TRISB 02C6 TRISB15 TRISB14 TRISB13 TRISB12 (1) PORTB 02C8 RB15 RB14 RB13 RB12 (1) LATB 02CA LATB15 LATB14 LATB13 LATB12 (1) ODCB 06C6 ...
Page 39
TABLE 3-20: PORTE REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISE 02D8 — — — — PORTE 02DA — — — — LATE 02DC — — — — ODCE 06D8 — — — — ...
Page 40
TABLE 3-24: PARALLEL MASTER/SLAVE PORT REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 PMCON 0600 PMPEN — PSIDL ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN PMMODE 0602 BUSY IRQM1 IRQM0 INCM1 (1) PMADDR CS2 CS1 0604 (1) ...
Page 41
TABLE 3-27: CRC REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 CRCCON 0640 — — CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT CRCXOR 0642 CRCDAT 0644 CRCWDAT 0646 Legend: — = unimplemented, read as ...
Page 42
... PIC24FJ128GA010 FAMILY 3.2.5 SOFTWARE STACK In addition to its use as a working register, the W15 reg- ister in PIC24F devices is also used as a Software Stack Pointer. The pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack pops and post-increments for stack pushes, as shown in Figure 3-4 ...
Page 43
... Note 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY Program Space Address <23> <22:16> 0 0xx xxxx xxxx xxxx xxxx xxx0 TBLPAG< ...
Page 44
... PIC24FJ128GA010 FAMILY 3.3.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space, without going through data space. The TBLRDH and TBLWTH instruc- tions are the only method to read or write the upper 8 bits of a program space word as data ...
Page 45
... Microchip Technology Inc. PIC24FJ128GA010 FAMILY 24-bit program word are used to contain the data. The upper 8 bits of any program space locations used as data should be programmed with ‘1111 ‘0000 0000’ to force a NOP. This prevents possible issues should the area of code ever be accidentally executed ...
Page 46
... PIC24FJ128GA010 FAMILY NOTES: DS39747E-page 46 © 2009 Microchip Technology Inc. ...
Page 47
... Enhanced In-Circuit Serial (Enhanced ICSP) ICSP allows a PIC24FJ128GA010 family device to be serially programmed while in the end application circuit. This is simply done with two lines for Programming Clock and Programming Data (which are named PGCx and PGDx, respectively), and three other lines for ...
Page 48
... PIC24FJ128GA010 FAMILY 4.2 RTSP Operation The PIC24F Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user to erase blocks of eight rows (512 instructions time and to program one row at a time also possible to program single words. The 8-row erase blocks and single row write blocks are ...
Page 49
... Memory row program operation (ERASE = operation (ERASE = 1) Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP3:NVMOP0 are unimplemented. 3: Available in ICSP™ mode only. Refer to device programming specification. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY (1) U-0 U-0 — — (1) U-0 ...
Page 50
... PIC24FJ128GA010 FAMILY 4.6.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY The user can program one row of program Flash memory at a time this necessary to erase the 8-row erase block containing the desired row. The general process is: 1. Read eight rows of program (512 instructions) and store in data RAM. ...
Page 51
... W0, NVMKEY MOV #0xAA, W1 MOV W1, NVMKEY BSET NVMCON, #WR BTSC NVMCON, #15 BRA $-2 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY ; ; Initialize NVMCON ; ; Initialize PM Page Boundary SFR ; An example program memory address ; ; ; Write PM low word into program latch ; Write PM high byte into program latch ; ; ; Write PM low word into program latch ...
Page 52
... PIC24FJ128GA010 FAMILY 4.6.2 PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY If a Flash location has been erased, it can be pro- grammed using table write instructions to write an instruction word (24-bit) into the write latch. The TBLPAG register is loaded with the 8 Most Significant Bytes of the Flash address. The TBLWTL and TBLWTH ...
Page 53
... Enable Voltage Regulator Trap Conflict Illegal Opcode Uninitialized W Register Configuration Word Mismatch Reset © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY Note: Refer to the specific peripheral or CPU section of this manual for register Reset states. All types of device Reset will set a corresponding status bit in the RCON register to indicate the type of Reset (see Register 5-1) ...
Page 54
... PIC24FJ128GA010 FAMILY REGISTER 5-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-0 U-0 TRAPR IOPUWR — bit 15 R/W-0 R/W-0 R/W-0 EXTR SWR SWDTEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TRAPR: Trap Reset Flag bit Trap Conflict Reset has occurred ...
Page 55
... Reset Type Clock Source Determinant POR Oscillator Configuration bits (FNOSC2:FNOSC0) BOR MCLR COSC Control bits (OSCCON<14:12>) WDTR SWR © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY Setting Event POR POR POR POR PWRSAV instruction, POR POR POR — — 5.2 Device Reset Times The Reset times for various types of device Reset are summarized in Table 5-3 ...
Page 56
... PIC24FJ128GA010 FAMILY TABLE 5-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS Reset Type Clock Source POR EC, FRC, FRCDIV, LPRC T ECPLL, FRCPLL XT, HS, SOSC XTPLL, HSPLL BOR EC, FRC, FRCDIV, LPRC ECPLL, FRCPLL XT, HS, SOSC XTPLL, HSPLL MCLR Any Clock WDT Any Clock ...
Page 57
... PLL to stabilize. In most cases, the FSCM delay will prevent an oscillator failure trap at a device Reset when the PWRT is disabled. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 5.3 Special Function Register Reset States Most of the Special Function Registers (SFRs) associ- ated with the PIC24F CPU and peripherals are reset to a particular value at a device Reset ...
Page 58
... PIC24FJ128GA010 FAMILY NOTES: DS39747E-page 58 © 2009 Microchip Technology Inc. ...
Page 59
... For example, the interrupt asso- ciated with vector 0 will take priority over interrupts at any other vector address. PIC24FJ128GA010 family devices implement non- maskable traps and unique interrupts. These are summarized in Table 6-1 and Table 6-2. © 2009 Microchip Technology Inc. ...
Page 60
... PIC24FJ128GA010 FAMILY FIGURE 6-1: PIC24F INTERRUPT VECTOR TABLE Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 — ...
Page 61
... SPI1 Event SPI2 Error SPI2 Event Timer1 Timer2 Timer3 Timer4 Timer5 UART1 Error UART1 Receiver UART1 Transmitter UART2 Error UART2 Receiver UART2 Transmitter © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY Vector AIVT IVT Address Number Address 13 00002Eh 00012Eh 18 000038h 000138h 67 00009Ah 00019Ah ...
Page 62
... PIC24FJ128GA010 FAMILY 6.3 Interrupt Control and Status Registers The PIC24FJ128GA010 family devices implement a total of 28 registers for the interrupt controller: • INTCON1 • INTCON2 • IFS0 through IFS4 • IEC0 through IEC4 • IPC0 through IPC14, and IPC16 Global interrupt control functions are controlled from INTCON1 and INTCON2 ...
Page 63
... See Register 2-2 for the description of remaining bit(s) that are not dedicated to interrupt control functions. 2: The IPL3 bit is concatenated with the IPL2:IPL0 bits (SR<7:5>) to form the CPU interrupt priority level. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY U-0 U-0 — — ...
Page 64
... PIC24FJ128GA010 FAMILY REGISTER 6-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 U-0 U-0 NSTDIS — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled ...
Page 65
... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY U-0 U-0 U-0 — — — R/W-0 ...
Page 66
... PIC24FJ128GA010 FAMILY REGISTER 6-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 U-0 R/W-0 — — AD1IF bit 15 R/W-0 R/W-0 R/W-0 T2IF OC2IF IC2IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13 ...
Page 67
... Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY R/W-0 R/W-0 R/W-0 T5IF T4IF OC4IF R/W-0 ...
Page 68
... PIC24FJ128GA010 FAMILY REGISTER 6-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 U-0 U-0 R/W-0 — — PMPIF bit 15 R/W-0 R/W-0 R/W-0 IC5IF IC4IF IC3IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13 ...
Page 69
... Interrupt request has not occurred bit 1 SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY U-0 U-0 U-0 — — — U-0 ...
Page 70
... PIC24FJ128GA010 FAMILY REGISTER 6-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-4 Unimplemented: Read as ‘0’ bit 3 ...
Page 71
... IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE U-0 ...
Page 72
... PIC24FJ128GA010 FAMILY REGISTER 6-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 U2TXIE U2RXIE INT2IE bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 U2TXIE: UART2 Transmitter Interrupt Enable bit ...
Page 73
... SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SPF2IE: SPI2 Fault Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY U-0 U-0 U-0 — — — U-0 ...
Page 74
... PIC24FJ128GA010 FAMILY REGISTER 6-13: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 R/W-0 U-0 — RTCIE — bit 15 U-0 R/W-0 R/W-0 — INT4IE INT3IE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIE: Real-Time Clock/Calendar Interrupt Enable bit ...
Page 75
... Interrupt request enabled 0 = Interrupt request not enabled bit 1 U1ERIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY U-0 U-0 U-0 — — — U-0 R/W-0 R/W-0 — ...
Page 76
... PIC24FJ128GA010 FAMILY REGISTER 6-15: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 — T1IP2 T1IP1 bit 15 U-0 R/W-1 R/W-0 — IC1IP2 IC1IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 ...
Page 77
... IC2IP2:IC2IP0: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY R/W-0 U-0 R/W-1 T2IP0 — OC2IP2 R/W-0 U-0 U-0 IC2IP0 — ...
Page 78
... PIC24FJ128GA010 FAMILY REGISTER 6-17: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 — U1RXIP2 U1RXIP1 bit 15 U-0 R/W-1 R/W-0 — SPF1IP2 SPF1IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 ...
Page 79
... Unimplemented: Read as ‘0’ bit 2-0 U1TXIP2:U1TXIP0: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 AD1IP0 — ...
Page 80
... PIC24FJ128GA010 FAMILY REGISTER 6-19: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 — CNIP2 CNIP1 bit 15 U-0 R/W-1 R/W-0 — MI2C1IP2 MI2C1IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 ...
Page 81
... Unimplemented: Read as ‘0’ bit 2-0 INT1IP2:INT1IP0: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY U-0 U-0 U-0 — — — U-0 U-0 R/W-1 — ...
Page 82
... PIC24FJ128GA010 FAMILY REGISTER 6-21: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 U-0 R/W-1 R/W-0 — T4IP2 T4IP1 bit 15 U-0 R/W-1 R/W-0 — OC3IP2 OC3IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 ...
Page 83
... Unimplemented: Read as ‘0’ bit 2-0 T5IP2:T5IP0: Timer5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY R/W-0 U-0 R/W-1 U2TXIP0 — U2RXIP2 R/W-0 U-0 R/W-1 INT2IP0 — ...
Page 84
... PIC24FJ128GA010 FAMILY REGISTER 6-23: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — SPI2IP2 SPI2IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 ...
Page 85
... IC3IP2:IC3IP0: Input Capture Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY R/W-0 U-0 R/W-1 IC5IP0 — IC4IP2 R/W-0 U-0 U-0 IC3IP0 — ...
Page 86
... PIC24FJ128GA010 FAMILY REGISTER 6-25: IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — OC5IP2 OC5IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 ...
Page 87
... SI2C2IP2:SI2C2IP0: Slave I2C2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY U-0 U-0 R/W-1 — — MI2C2IP2 R/W-0 U-0 U-0 SI2C2IP0 — ...
Page 88
... PIC24FJ128GA010 FAMILY REGISTER 6-28: IPC13: INTERRUPT PRIORITY CONTROL REGISTER 13 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — INT3IP2 INT3IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 ...
Page 89
... RTCIP2:RTCIP0: Real-Time Clock/Calendar Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY U-0 U-0 R/W-1 — — RTCIP2 U-0 U-0 U-0 — ...
Page 90
... PIC24FJ128GA010 FAMILY REGISTER 6-30: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 R/W-1 R/W-0 — CRCIP2 CRCIP1 bit 15 U-0 R/W-1 R/W-0 — U1ERIP2 U1ERIP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 ...
Page 91
... RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 6.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, except that the appropriate trap status flag in the INTCON1 register must be cleared to avoid re-entry into the TSR ...
Page 92
... PIC24FJ128GA010 FAMILY NOTES: DS39747E-page 92 © 2009 Microchip Technology Inc. ...
Page 93
... Refer to Section 6. “Oscillator” (DS39700) in the “PIC24F Reference Manual” for more information. The oscillator system for PIC24FJ128GA010 family devices has the following features: • A total of four external and internal oscillator options as clock sources, providing 11 different clock modes FIGURE 7-1: PIC24FJ128GA010 FAMILY CLOCK DIAGRAM ...
Page 94
... PIC24FJ128GA010 FAMILY 7.1 CPU Clocking Scheme The system clock source can be provided by one of four sources: • Primary Oscillator (POSC) on the OSC1 and OSC2 pins • Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins • Fast Internal RC (FRC) Oscillator • Low-Power Internal RC (LPRC) Oscillator The primary oscillator and FRC sources have the option of using the internal 4x PLL ...
Page 95
... Also resets to ‘0’ during any valid clock switch, or whenever a non-PLL Clock mode is selected. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY The Clock Divider register (Register 7-2) controls the features associated with Doze mode, as well as the postscaler for the FRC oscillator. ...
Page 96
... PIC24FJ128GA010 FAMILY REGISTER 7-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 5 LOCK: PLL Lock Status bit 1 = PLL module is in lock or PLL module start-up timer is satisfied 0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled bit 4 Unimplemented: Read as ‘0’ bit 3 CF: Clock Fail Detect bit ...
Page 97
... MHz (divide by 4) 001 = 4 MHz (divide by 2) 000 = 8 MHz (divide by 1) bit 7-0 Unimplemented: Read as ‘0’ Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY R/W-0 R/W-0 R/W-0 (1) DOZE0 DOZEN RCDIV2 ...
Page 98
... PIC24FJ128GA010 FAMILY REGISTER 7-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-0 — — TUN5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 ...
Page 99
... OSCCON register low byte. 5. Set the OSWEN bit to initiate the oscillator switch. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY Once the basic sequence is completed, the system clock hardware responds automatically as follows: 1. The clock switching hardware compares the COSC status bits with the new value of the NOSC control bits ...
Page 100
... PIC24FJ128GA010 FAMILY A recommended code sequence for a clock switch includes the following: 1. Disable interrupts during the OSCCON register unlock and write sequence. 2. Execute the unlock sequence for the OSCCON high byte, by writing 78h and 9Ah to OSCCON<15:8> in two instructions. 3. Write new oscillator source to the NOSC control bits in the instruction immediately following the unlock sequence ...
Page 101
... Refer to Section 10. Power- Saving Features” (DS39698) in the “PIC24F Family Reference Manual” for more information. The PIC24FJ128GA010 family of devices provide the ability to manage power consumption by selectively managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power ...
Page 102
... PIC24FJ128GA010 FAMILY 8.2.2 IDLE MODE Idle mode has these features: • The CPU will stop executing instructions. • The WDT is automatically cleared. • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 8.4 “ ...
Page 103
... Data Latch Read LAT Read PORT © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled ...
Page 104
... DS39747E-page 104 9.3 Input Change Notification The input change notification function of the I/O ports allows the PIC24FJ128GA010 family of devices to gen- erate interrupt requests to the processor in response to a change-of-state on selected input pins. This feature is capable of detecting input change-of-states even in Sleep mode, when the clocks are disabled. Depending ...
Page 105
... T1CK SOSCI TGATE 1 Set T1IF 0 Reset Equal © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY Figure 10-1 presents a block diagram of the 16-bit timer module. To configure Timer1 for operation: 1. Set the TON bit (= 1). 2. Select the timer prescaler ratio using the TCKPS1:TCKPS0 bits. ...
Page 106
... PIC24FJ128GA010 FAMILY REGISTER 10-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE TCKPS1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Read as ‘ ...
Page 107
... Timer2 and Timer4 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the Timer3 or Timer5 interrupt flags. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY To configure Timer2/3 or Timer4/5 for 32-bit operation: 1. Set the T32 bit (T2CON<3> or T4CON<3> ...
Page 108
... PIC24FJ128GA010 FAMILY FIGURE 11-1: TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM T2CK (T4CK) TGATE 1 Set T3IF (T5IF) 0 ADC Event Trigger* Equal MSB Reset Read TMR2 (TMR4) Write TMR2 (TMR4) Data Bus<15:0> Note: The 32-bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON and T4CON registers ...
Page 109
... Equal FIGURE 11-3: TIMER3 AND TIMER5 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM T3CK (T5CK) TGATE 1 Set T3IF (T5IF) 0 Reset ADC Event Trigger* Equal * The ADC Event Trigger is available only on Timer4/5. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 1x Gate Sync TMR2 (TMR4) Sync Comparator ...
Page 110
... PIC24FJ128GA010 FAMILY REGISTER 11-1: TxCON: TIMER2 AND TIMER4 CONTROL REGISTER R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE TCKPS1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TON: Timerx On bit When TxCON<3> ...
Page 111
... External clock from pin TyCK (on the rising edge Internal clock (F OSC bit 0 Unimplemented: Read as ‘0’ Note 1: When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timery operation; all timer functions are set through T2CON. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY U-0 U-0 (1) — — R/W-0 U-0 (1) ...
Page 112
... PIC24FJ128GA010 FAMILY NOTES: DS39747E-page 112 © 2009 Microchip Technology Inc. ...
Page 113
... System Bus Note: An ‘x’ signal, register or bit name denotes the number of the capture channel. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY • Capture timer value on every fourth rising edge of input applied at the ICx pin • Capture timer value on every 16th rising edge of input applied at the ICx pin • ...
Page 114
... PIC24FJ128GA010 FAMILY 12.1 Input Capture Registers REGISTER 12-1: ICxCON: INPUT CAPTURE x CONTROL REGISTER U-0 U-0 R/W-0 — — ICSIDL bit 15 R/W-0 R/W-0 R/W-0 (1) ICTMR ICI1 ICI0 bit 7 Legend Hardware Clearable R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘ ...
Page 115
... Dual Compare Match mode generating: - Single Output Pulse mode - Continuous Output Pulse mode • Simple Pulse-Width Modulation mode: - with Fault protection input - without Fault protection input © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY Set Flag bit (1) OCxIF Output S Q Logic ...
Page 116
... PIC24FJ128GA010 FAMILY To generate a single output pulse, the following steps are required (these steps assume the timer source is initially turned off, but this is not a requirement for the module operation): 1. Determine the instruction clock cycle time. Take into account the frequency of the external clock to the timer source (if one is used) and the timer prescaler settings ...
Page 117
... Equation 13-1. EQUATION 13-2: CALCULATION FOR MAXIMUM PWM RESOLUTION Maximum PWM Resolution (bits) = Note 1: Based on F © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY EQUATION 13-1: PWM Period = [(PRy • T where: PWM Frequency = 1/[PWM Period] Note 1: Based on T PLL are disabled. ...
Page 118
... PIC24FJ128GA010 FAMILY EXAMPLE 13-1: PWM PERIOD AND DUTY CYCLE CALCULATIONS 1. Find the Period register value for a desired PWM frequency of 52.08 kHz, where F clock rate) and a Timer2 prescaler setting of 1: 2 OSC PWM Period = 1/PWM Frequency = 1/52.08 kHz = 19.2 μs PWM Period = (PR2 + 1) • 19.2 μ ...
Page 119
... Output compare channel is disabled Note 1: Refer to the device data sheet for specific time bases available to the output compare module. 2: OCFA pin controls OC1-OC4 channels. OCFB pin controls the OC5 channel. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY U-0 U-0 U-0 — — ...
Page 120
... PIC24FJ128GA010 FAMILY NOTES: DS39747E-page 120 © 2009 Microchip Technology Inc. ...
Page 121
... SPI1 and SPI2. Special Function Reg- isters will follow a similar notation. For example, SPIxCON refers to the control register for the SPI1 or SPI2 module. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY To set up the SPI module for the Standard Master mode of operation using interrupts: ...
Page 122
... PIC24FJ128GA010 FAMILY To set up the SPI module for the Enhanced Buffer Master mode of operation using interrupts: a) Clear the SPIxIF bit in the respective IFSx register. b) Set the SPIxIE bit in the respective IECx register. c) Write the SPIxIP bits in the respective IPCx register. 2. Write the desired settings to the SPIxCON1 and ...
Page 123
... Control Control Clock SDOx bit0 SDIx SPIxSR Transfer 8-Level FIFO Receive Buffer SPIxBUF Read SPIxBUF © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 1:1 to 1:8 Secondary Prescaler Select Edge Shift Control Transfer 8-Level FIFO Transmit Buffer Write SPIxBUF 16 Internal Data Bus 1:1/4/16/64 ...
Page 124
... PIC24FJ128GA010 FAMILY REGISTER 14-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 SPIEN — SPISIDL bit 15 R/W-0 R/C-0 R/W-0 SRMPT SPIROV SRXMPT bit 7 Legend Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 SPIEN: SPIx Enable bit ...
Page 125
... SPIxBUF location, reading SPIxRXB. In Enhanced Buffer mode: Automatically set in hardware when SPIx transfers data from SPIxSR to buffer, filling the last unread buffer location. Automatically cleared in hardware when a buffer location is available for a transfer from SPIxSR. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY DS39747E-page 125 ...
Page 126
... PIC24FJ128GA010 FAMILY REGISTER 14-2: SPI CON1: SPIx CONTROL REGISTER 1 X U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 SSEN CKP MSTEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ ...
Page 127
... Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 SPIBEN: Enhanced Buffer Enable bit 1 = Enhanced Buffer enabled 0 = Enhanced Buffer disabled (Legacy mode) © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY U-0 U-0 U-0 — — — ...
Page 128
... PIC24FJ128GA010 FAMILY FIGURE 14-3: SPI MASTER/SLAVE CONNECTION (STANDARD MODE) PROCESSOR 1 (SPI Master) Serial Receive Buffer (SPIxRXB) Shift Register (SPIxSR) MSb Serial Transmit Buffer (SPIxTXB) SPIx Buffer (SPIxBUF) (MSTEN (SPIxCON1<5> = 1)) Note 1: Using the SSx pin in the Slave mode of operation is optional. 2: User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory mapped to SPIxBUF ...
Page 129
... FIGURE 14-7: SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM PIC24F (SPI Slave, Frame Slave) FIGURE 14-8: SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM PIC24F (SPI Master, Frame Slave) © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY PROCESSOR 2 SDOx SDIx SDIx SDOx Serial Clock SCKx SCKx ...
Page 130
... PIC24FJ128GA010 FAMILY EQUATION 14-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED F SCK Note 1: Based TABLE 14-1: SAMPLE SCK FREQUENCIES MHz CY Primary Prescaler Settings MHz CY Primary Prescaler Settings Note 1: Based /2, Doze mode and PLL are disabled. CY OSC 2: SCKx frequencies shown in kHz. DS39747E-page 130 ...
Page 131
... Bus Repeater mode, allowing the acceptance of all messages as a slave regardless of the address • Automatic SCL A block diagram of the module is shown in Figure 15-1. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 15.1 Communicating as a Master in a Single Master Environment The details of sending a message in Master mode depends on the communications protocol for the device being communicated with ...
Page 132
... PIC24FJ128GA010 FAMILY 2 FIGURE 15-1: I C™ BLOCK DIAGRAM Shift SCLx Clock SDAx Shift Clock BRG Down Counter DS39747E-page 132 I2CxRCV I2CxRSR LSB Address Match Match Detect I2CxADD Start and Stop Bit Detect Start and Stop Bit Generation Collision Detect Acknowledge Generation ...
Page 133
... Address will be Acknowledged only if GCEN = 1. 3: Match on this address can only occur on the upper byte in 10-Bit Addressing mode. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 15.3 Slave Address Masking The I2CxMSK register (Register 15-3) designates address bit positions as “don’t care” for both 7-Bit and 10-Bit Addressing modes ...
Page 134
... PIC24FJ128GA010 FAMILY REGISTER 15-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 I2CEN — I2CSIDL bit 15 R/W-0 R/W-0 R/W-0 GCEN STREN ACKDT bit 7 Legend Hardware Clearable R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 I2CEN: I2Cx Enable bit 1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins 0 = Disables I2Cx module ...
Page 135
... SEN: Start Condition Enabled bit (when operating Initiate Start condition on SDA and SCL pins. Hardware clear at end of master Start sequence Start condition not in progress © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 2 C master. Applicable during master receive.) C master. Applicable during master receive.) ...
Page 136
... PIC24FJ128GA010 FAMILY REGISTER 15-2: I2CxSTAT: I2Cx STATUS REGISTER R-0, HSC R-0, HSC U-0 ACKSTAT TRSTAT — bit 15 R/C-0, HSC R/C-0, HSC R-0, HSC IWCOL I2COV D/A bit 7 Legend Hardware Settable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set ...
Page 137
... Hardware set when I2CxRCV written with received byte. Hardware clear when software reads I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 2 C slave device address byte. DS39747E-page 137 ...
Page 138
... PIC24FJ128GA010 FAMILY REGISTER 15-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 AMSK7 AMSK6 AMSK5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-10 Unimplemented: Read as ‘0’ ...
Page 139
... Baud Rate Generator Hardware Flow Control UARTx Receiver UARTx Transmitter © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY • Fully Integrated Baud Rate Generator with 16-Bit Prescaler • Baud Rates Ranging from 1 Mbps to 15 bps at 16 MIPS • 4-Deep First-In-First-Out (FIFO) Transmit Data Buffer • ...
Page 140
... PIC24FJ128GA010 FAMILY 16.1 UART Baud Rate Generator (BRG) The UART module includes a dedicated 16-bit Baud Rate Generator. The BRGx register controls the period of a free-running, 16-bit timer. Equation 16-1 shows the formula for computation of the baud rate with BRGH = 0. EQUATION 16-1: ...
Page 141
... FIFO. 5. After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 16.5 Receiving in 8-Bit or 9-Bit Data Mode 1. Set up the UART (as described in Section 16.2 “Transmitting in 8-Bit Data Mode”). ...
Page 142
... PIC24FJ128GA010 FAMILY REGISTER 16-1: UxMODE: UARTx MODE REGISTER R/W-0 U-0 R/W-0 UARTEN — USIDL bit 15 R/W-0, HC R/W-0 R/W-0, HC WAKE LPBACK ABAUD bit 7 Legend Hardware Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 UARTEN: UARTx Enable bit 1 = UARTx is enabled ...
Page 143
... STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit Note 1: This feature is only available for the 16x BRG mode (BRGH = 0). © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY DS39747E-page 143 ...
Page 144
... PIC24FJ128GA010 FAMILY REGISTER 16-2: UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 UTXISEL1 TXINV UTXISEL0 bit 15 R/W-0 R/W-0 R/W-0 URXISEL1 URXISEL0 ADDEN bit 7 Legend Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15,13 UTXISEL1:UTXISEL0: Transmission Interrupt Mode Selection bits 11 = Reserved ...
Page 145
... Receive buffer has not overflowed (clearing a previously set OERR bit (1 → 0 transition) will reset the receiver buffer and the RSR to the empty state) bit 0 URXDA: Receive Buffer Data Available bit (read-only Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY DS39747E-page 145 ...
Page 146
... PIC24FJ128GA010 FAMILY NOTES: DS39747E-page 146 © 2009 Microchip Technology Inc. ...
Page 147
... FIGURE 17-1: PMP MODULE OVERVIEW PIC24F Parallel Master Port © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY Key features of the PMP module include: • Programmable Address Lines • Two Chip Select Lines • Programmable Strobe Options - Individual Read and Write Strobes or; ...
Page 148
... PIC24FJ128GA010 FAMILY REGISTER 17-1: PMCON: PARALLEL PORT CONTROL REGISTER R/W-0 U-0 R/W-0 PMPEN — PSIDL bit 15 (1) R/W-0 R/W-0 R/W-0 CSF1 CSF0 ALP bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 PMPEN: Parallel Master Port Enable bit ...
Page 149
... Read strobe active-high (PMRD Read strobe active-low (PMRD) For Master mode 1 (PMMODE<9:8> Read/write strobe active-high (PMRD/PMWR Read/write strobe active-low (PMRD/PMWR) Note 1: These bits have no effect when their corresponding pins are used as address lines. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY DS39747E-page 149 ...
Page 150
... PIC24FJ128GA010 FAMILY REGISTER 17-2: PMMODE: PARALLEL PORT MODE REGISTER R-0 R/W-0 R/W-0 BUSY IRQM1 IRQM0 bit 15 R/W-0 R/W-0 R/W-0 (1) (1) WAITB1 WAITB0 WAITM3 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 BUSY: Busy bit (Master mode only) ...
Page 151
... PMA<13:2> function as PMP address lines 0 = PMA<13:2> function as port I/O bit 1-0 PTEN1:PTEN0: PMALH/PMALL Strobe Enable bits 1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL 0 = PMA1 and PMA0 pads functions as port I/O © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY (1) R/W-0 R/W-0 R/W-0 ADDR<13:8> R/W-0 ...
Page 152
... PIC24FJ128GA010 FAMILY REGISTER 17-5: PMSTAT: PARALLEL PORT STATUS REGISTER R-0 R/W-0, HS U-0 IBF IBOV — bit 15 R-1 R/W-0, HS U-0 OBE OBUF — bit 7 Legend Hardware Settable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 IBF: Input Buffer Full Status bit ...
Page 153
... PMP module uses TTL input buffers 0 = PMP module uses Schmitt input buffers Note 1: To enable the actual RTCC output, the RTCCFG (RTCOE) bit needs to be set. 2: Refer to Table 1-2 for affected PMP inputs. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY U-0 U-0 U-0 — — — ...
Page 154
... PIC24FJ128GA010 FAMILY FIGURE 17-2: LEGACY PARALLEL SLAVE PORT EXAMPLE Master PMD<7:0> PMCS PMRD PMWR FIGURE 17-3: ADDRESSABLE PARALLEL SLAVE PORT EXAMPLE Master PMA<1:0> PMD<7:0> PMCS PMRD PMWR Address Bus Data Bus Control Lines TABLE 17-1: SLAVE MODE ADDRESS RESOLUTION PMA<1:0> Output Register (Buffer) 00 PMDOUT1< ...
Page 155
... PMALL PMALH PMCS1 PMRD PMWR FIGURE 17-8: EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION PIC24F PMD<7:0> PMALL PMA<14:7> PMCS1 PMRD PMWR © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY PMA<13:8> PMD<7:0> PMA<7:0> PMCS1 PMCS2 PMALL PMRD PMWR PMD<7:0> PMA<13:8> PMCS1 PMCS2 PMALL PMALH ...
Page 156
... PIC24FJ128GA010 FAMILY FIGURE 17-9: EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATION PIC24F PMD<7:0> PMALL PMCS1 PMRD PMWR FIGURE 17-10: PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 8-BIT DATA) PIC24F PMA<n:0> PMD<7:0> PMCS1 PMRD PMWR FIGURE 17-11: PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 16-BIT DATA) PIC24F PMA< ...
Page 157
... Event Comparator Compare Registers with Masks Repeat Counter © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY • 24-Hour Format (Military Time) • Calendar: Weekday, Date, Month and Year • Alarm Configurable • Year Range: 2000 to 2099 • Leap Year Correction • BCD Format for Compact Firmware • ...
Page 158
... PIC24FJ128GA010 FAMILY 18.1 RTCC Module Registers The RTCC module registers are organized into three categories: • RTCC Control Registers • RTCC Value Registers • Alarm Value Registers 18.1.1 REGISTER MAPPING To limit the register interface, the RTCC Timer and Alarm Time registers are accessed through corre- sponding register pointers ...
Page 159
... The RCFGCAL Reset value is dependent on type of Reset write to the RTCEN bit is only allowed when RTCWREN = 1. 3: This bit is read-only cleared to ‘0’ write to the lower half of the MINSEC register. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY R-0 R-0 R/W-0 (3) RTCSYNC HALFSEC ...
Page 160
... PIC24FJ128GA010 FAMILY REGISTER 18-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER bit 7-0 CAL7:CAL0: RTC Drift Calibration bits 01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every one minute ... 01111111 = Minimum positive adjustment; adds 4 RTC clock pulses every one minute 00000000 = No adjustment 11111111 = Minimum negative adjustment ...
Page 161
... Alarm will repeat 255 more times ... 00000000 = Alarm will not repeat The counter decrements on any alarm event. The counter is prevented from rolling over from 00h to FFh unless CHIME = 1. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY R/W-0 R/W-0 R/W-0 AMASK2 AMASK1 ...
Page 162
... PIC24FJ128GA010 FAMILY 18.1.4 RTCVAL REGISTER MAPPINGS REGISTER 18-4: YEAR: YEAR VALUE REGISTER U-0 U-0 U-0 — — — bit 15 R/W-x R/W-x R/W-x YRTEN3 YRTEN2 YRTEN1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-8 Unimplemented: Read as ‘0’ ...
Page 163
... Unimplemented: Read as ‘0’ bit 6-4 SECTEN2:SECTEN0: Binary Coded Decimal Value of Second’s Tens Digit; Contains a value from bit 3-0 SECONE3:SECONE0: Binary Coded Decimal Value of Second’s Ones Digit; Contains a value from © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY U-0 U-0 R/W-x — — ...
Page 164
... PIC24FJ128GA010 FAMILY 18.1.5 ALRMVAL REGISTER MAPPINGS REGISTER 18-8: ALMTHDY: ALARM MONTH AND DAY VALUE REGISTER U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-x — — DAYTEN1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘ ...
Page 165
... Unimplemented: Read as ‘0’ bit 6-4 SECTEN2:SECTEN0: Binary Coded Decimal Value of Second’s Tens Digit; Contains a value from bit 3-0 SECONE3:SECONE0: Binary Coded Decimal Value of Second’s Ones Digit; Contains a value from © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY R/W-x R/W-x R/W-x MINTEN0 MINONE3 ...
Page 166
... PIC24FJ128GA010 FAMILY 18.2 Calibration The real-time crystal input can be calibrated using the periodic auto-adjust feature. When properly calibrated, the RTCC can provide an error of less than 3 seconds per month. This is accomplished by finding the number of error clock pulses and storing the value into the lower half of the RCFGCAL register ...
Page 167
... Every 10 minutes 0101 – Every hour 0110 – Every day 0111 – Every week 1000 – Every month (1) 1001 – Every year Note 1: Annually, except when configured for February 29. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY Day of the Week Month Day Hours ...
Page 168
... PIC24FJ128GA010 FAMILY NOTES: DS39747E-page 168 © 2009 Microchip Technology Inc. ...
Page 169
... IN BIT 0 D OUT 1 p_clk © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 19.2 Overview The module implements a software configurable CRC generator. The terms of the polynomial and its length can be programmed using the CRCXOR (X<15:1>) bits and the CRCCON (PLEN3:PLEN0) bits, respectively. Consider the following equation: ...
Page 170
... PIC24FJ128GA010 FAMILY FIGURE 19-2: CRC GENERATOR RECONFIGURED FOR x XOR SDOx BIT 0 BIT 4 p_clk p_clk 19.3 User Interface 19.3.1 DATA INTERFACE To start serial shifting, a ‘1’ must be written to the CRCGO bit. The module incorporates a FIFO that is 8 deep when PLEN (PLEN<3:0>) > 7, and 16 deep otherwise. The data for which the CRC calculated must first be written into the FIFO ...
Page 171
... Operation in Power Save Modes 19.4.1 SLEEP MODE If Sleep mode is entered while the module is operating, the module will be suspended in its current state until clock execution resumes. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY R-0 R-0 R-0 VWORD4 VWORD3 VWORD2 R/W-0 R/W-0 ...
Page 172
... PIC24FJ128GA010 FAMILY NOTES: DS39747E-page 172 © 2009 Microchip Technology Inc. ...
Page 173
... The actual number of analog input pins and external voltage reference input configuration will depend on the specific device. Refer to the device data sheet for further details. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY A block diagram of the A/D Converter is shown in Figure 20-1. To perform an A/D conversion: 1. ...
Page 174
... PIC24FJ128GA010 FAMILY 10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM Figure 20- REF REF AN0 AN1 V INH AN2 AN3 AN4 AN5 V INL AN6 AN7 AN8 AN9 V AN10 AN11 AN12 V AN13 AN14 AN15 DS39747E-page 174 V INH S/H DAC V INL 10-Bit SAR Data Formatting ADC1BUF0: ADC1BUFF ...
Page 175
... SAMP: A/D Sample Enable bit 1 = A/D sample/hold amplifier is sampling input 0 = A/D sample/hold amplifier is holding bit 0 DONE: A/D Conversion Status bit 1 = A/D conversion is done 0 = A/D conversion is NOT done © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY U-0 U-0 U-0 — — — U-0 ...
Page 176
... PIC24FJ128GA010 FAMILY REGISTER 20-2: AD1CON2: A/D CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 VCFG2 VCFG1 VCFG0 bit 15 R-0 U-0 R/W-0 BUFS — SMPI3 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 VCFG2:VCFG0: Voltage Reference Configuration bits: VCFG2:VCFG0 ...
Page 177
... AD bit 7-0 ADCS7:ADCS0: A/D Conversion Clock Select bits 11111111 = 256 • ······ 00000001 = 00000000 = T CY © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY R/W-0 R/W-0 R/W-0 SAMC4 SAMC3 SAMC2 R/W-0 R/W-0 R/W-0 ADCS4 ADCS3 ADCS2 U = Unimplemented bit, read as ‘ ...
Page 178
... PIC24FJ128GA010 FAMILY REGISTER 20-4: AD1CHS: A/D INPUT SELECT REGISTER R/W-0 U-0 U-0 CH0NB — — bit 15 R/W-0 U-0 U-0 CH0NA — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 CH0NB: Channel 0 Negative Input Select for MUX B Multiplexer Setting bit ...
Page 179
... Value at POR ‘1’ = Bit is set bit 15-0 CSSL15:CSSL0: A/D Input Pin Scan Selection bits 1 = Corresponding analog channel selected for input scan 0 = Analog channel omitted from input scan © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY R/W-0 R/W-0 R/W-0 PCFG12 PCFG11 PCFG10 ...
Page 180
... PIC24FJ128GA010 FAMILY EQUATION 20-1: A/D CONVERSION CLOCK PERIOD Note 1: Based Doze mode and PLL are disabled. CY OSC FIGURE 20-2: 10-BIT A/D CONVERTER ANALOG INPUT MODEL ANx PIN 6-11 pF (Typical) Legend: C Note: C value depends on device package and is not tested. Effect of C PIN ...
Page 181
... Voltage Level © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY DS39747E-page 181 ...
Page 182
... PIC24FJ128GA010 FAMILY NOTES: DS39747E-page 182 © 2009 Microchip Technology Inc. ...
Page 183
... C2POS C2IN REF © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY The analog comparators that can be configured in a variety of ways. The inputs can be selected from the analog inputs multiplexed with I/O pins, as well as the on-chip voltage reference. Block diagrams of the various comparator configurations are shown in Figure 21-1. ...
Page 184
... PIC24FJ128GA010 FAMILY REGISTER 21-1: CMCON: COMPARATOR CONTROL REGISTER R/W-0 U-0 R/C-0 CMIDL — C2EVT bit 15 R-0 R-0 R/W-0 C2OUT C1OUT C2INV bit 7 Legend Clearable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 CMIDL: Stop in Idle Mode bit 1 = When device enters Idle mode, module does not generate interrupts ...
Page 185
... C1NEG: Comparator 1 Negative Input Configure bit 1 = Input is connected Input is connected to V See Figure 21-1 for the Comparator modes. bit 0 C1POS: Comparator 1 Positive Input Configure bit 1 = Input is connected Input is connected to CV See Figure 21-1 for the Comparator modes. © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY + REF + IN ...
Page 186
... PIC24FJ128GA010 FAMILY NOTES: DS39747E-page 186 © 2009 Microchip Technology Inc. ...
Page 187
... CVREN CVRR V - REF © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY voltage, each with 16 distinct levels. The range to be used is selected by the CVRR bit (CVRCON<5>). The primary difference between the ranges is the size of the steps selected (CVR3:CVR0), with one range offering finer resolution. ...
Page 188
... PIC24FJ128GA010 FAMILY REGISTER 22-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 CVREN CVROE CVRR bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-8 Unimplemented: Read as ‘0’ ...
Page 189
... CONSIDERATIONS FOR CONFIGURING PIC24FJ128GA010 FAMILY DEVICES In PIC24FJ128GA010 family devices, the configuration bytes are implemented as volatile memory. This means that configuration data must be programmed each time the device is powered up. Configuration data is stored in the two words at the top of the on-chip program memory space, known as the Flash Configuration Words ...
Page 190
... PIC24FJ128GA010 FAMILY REGISTER 23-1: FLASH CONFIGURATION WORD 1 U-1 U-1 U-1 — — — bit 23 r-x R/PO-1 R/PO-1 (1) r JTAGEN GCP bit 15 R/PO-1 R/PO-1 U-1 FWDTEN WINDIS — bit 7 Legend Readable bit PO = Program-Once bit -n = Value at POR ‘1’ = Bit is set bit 23-16 Unimplemented: Read as ‘ ...
Page 191
... Note 1: JTAGEN bit can not be modified using JTAG programming. It can only change using In-Circuit Serial Programming™ (ICSP™). © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY DS39747E-page 191 ...
Page 192
... PIC24FJ128GA010 FAMILY REGISTER 23-2: FLASH CONFIGURATION WORD 2 U-1 U-1 U-1 — — — bit 23 R/PO-1 U-1 U-1 IESO — — bit 15 R/PO-1 R/PO-1 R/PO-1 FCKSM1 FCKSM0 OSCIOFCN bit 7 Legend Readable bit PO = Program-Once bit -n = Value at POR ‘1’ = Bit is set bit 23-16 Unimplemented: Read as ‘ ...
Page 193
... PO = Program-Once bit -n = Value at POR ‘1’ = Bit is set bit 23-14 Unimplemented: Read as ‘0’ bit 13-6 FAMID7:FAMID0: Device Family Identifier bits 00010000 = PIC24FJ128GA010 family bit 5-0 DEV5:DEV0: Individual Device Identifier bits 000101 = PIC24FJ64GA006 000110 = PIC24FJ96GA006 000111 = PIC24FJ128GA006 001000 = PIC24FJ64GA008 001001 = PIC24FJ96GA008 ...
Page 194
... PIC24FJ128GA010 FAMILY REGISTER 23-4: DEVREV: DEVICE REVISION REGISTER — — — bit bit MAJRV1 MAJRV0 — bit 7 Legend Readable bit PO = Program-Once bit -n = Value at POR ‘1’ = Bit is set bit 23-16 Unimplemented: Read as ‘0’ bit 15-12 Reserved: For factory use only bit 11-9 Unimplemented: Read as ‘ ...
Page 195
... On-Chip Voltage Regulator All of the PIC24FJ128GA010 family devices power their core digital logic at a nominal 2.5V. This may create an issue for designs that are required to operate at a higher typical voltage, such as 3.3V. To simplify system design, all devices in the PIC24FJ128GA010 incorporate an on-chip regulator that allows the device to run its core logic from V ...
Page 196
... Timer (WDT)” (DS39697) in the “PIC24F Family Reference Manual” for more information. For PIC24FJ128GA010 family devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. The nominal WDT clock source from LPRC is 32 kHz. ...
Page 197
... Diagnostics” (DS39716) in the “PIC24F Family Reference Manual” for more information. For all devices in the PIC24FJ128GA010 family of devices, the on-chip program memory space is treated as a single block. Code protection for this block is con- trolled by one Configuration bit, GCP. This bit inhibits external reads and writes to the program memory space ...
Page 198
... PIC24FJ128GA010 FAMILY NOTES: DS39747E-page 198 © 2009 Microchip Technology Inc. ...
Page 199
... The bit in the W register or file register (specified by a literal value or indirectly by the contents of register ‘Wb’) © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY The literal instructions that involve data movement may use some of the following operands: • A literal value to be loaded into a W register or file register (specified by the value of ‘ ...
Page 200
... PIC24FJ128GA010 FAMILY TABLE 24-1: SYMBOLS USED IN OPCODE DESCRIPTIONS Field #text Means literal defined by “text” (text) Means “content of text” [text] Means “the location addressed by text” Optional field or operation <n:m> Register bit field .b Byte mode selection .d Double-Word mode selection .S Shadow register select ...