DSPIC30F3011-20I/ML Microchip Technology, DSPIC30F3011-20I/ML Datasheet - Page 31
![IC DSPIC MCU/DSP 24K 44QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
DSPIC30F3011-20I/ML
Manufacturer Part Number
DSPIC30F3011-20I/ML
Description
IC DSPIC MCU/DSP 24K 44QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F3010-30ISO.pdf
(228 pages)
2.DSPIC30F3010-30ISO.pdf
(18 pages)
3.DSPIC30F3010-30ISO.pdf
(6 pages)
4.DSPIC30F3010-30ISO.pdf
(16 pages)
5.DSPIC30F3010-30ISO.pdf
(22 pages)
6.DSPIC30F3010-20ISP.pdf
(226 pages)
Specifications of DSPIC30F3011-20I/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
30
Program Memory Size
24KB (8K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
30
Flash Memory Size
24KB
Supply Voltage Range
2.5V To 5.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F301120IML
- DSPIC30F3010-30ISO PDF datasheet
- DSPIC30F3010-30ISO PDF datasheet #2
- DSPIC30F3010-30ISO PDF datasheet #3
- DSPIC30F3010-30ISO PDF datasheet #4
- DSPIC30F3010-30ISO PDF datasheet #5
- DSPIC30F3010-20ISP PDF datasheet #6
- Current page: 31 of 228
- Download datasheet (4Mb)
FIGURE 3-5:
3.2
The core has two data spaces. The data spaces can be
considered either separate (for some DSP instruc-
tions), or as one unified linear address range (for MCU
instructions). The data spaces are accessed using two
Address Generation Units (AGUs) and separate data
paths.
3.2.1
The data space memory is split into two blocks, X and
Y data space. A key element of this architecture is that
Y space is a subset of X space, and is fully contained
within X space. In order to provide an apparent linear
addressing space, X and Y spaces have contiguous
addresses.
© 2010 Microchip Technology Inc.
Note: PSVPAG is an 8-bit register, containing bits<22:15> of the program space address
BSET
MOV
MOV
MOV
Space
Data
EA
Upper half of Data
Space is mapped
into Program Space
(i.e., it defines the page in program space to which the upper half of data space is being mapped).
Data Address Space
CORCON,#2
#0x00, W0
W0, PSVPAG
0x9200, W0
DATA SPACE MEMORY MAP
16
EA<15> = 0
EA<15> = 1
DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION
15
15
; PSV bit set
; Set PSVPAG register
; Access program memory location
; using a data space access
Data Space
0x8000
15
0xFFFF
0x0000
Address
Concatenation
PSVPAG
0x00
When executing any instruction other than one of the
MAC class of instructions, the X block consists of the
64 Kbyte data address space (including all Y
addresses). When executing one of the MAC class of
instructions, the X block consists of the 64 Kbyte data
address space excluding the Y address block (for data
reads only). In other words, all other instructions regard
the entire data memory as one composite address
space. The MAC class instructions extract the Y
address space from data space and address it using
EAs sourced from W10 and W11. The remaining X data
space is addressed using W8 and W9. Both address
spaces are concurrently accessed only with the MAC
class instructions.
A data space memory map is shown in
Figure 3-7
data spaces are accessed for MCU and DSP
instructions.
8
dsPIC30F3010/3011
(1)
23
shows a graphical summary of how X and Y
23
Program Space
Data Read
15
DS70141F-page 31
0
Figure
0x003FFE
0x000100
0x001200
3-6.
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