DSPIC30F3011-20I/ML Microchip Technology, DSPIC30F3011-20I/ML Datasheet - Page 134
![IC DSPIC MCU/DSP 24K 44QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
DSPIC30F3011-20I/ML
Manufacturer Part Number
DSPIC30F3011-20I/ML
Description
IC DSPIC MCU/DSP 24K 44QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F3010-30ISO.pdf
(228 pages)
2.DSPIC30F3010-30ISO.pdf
(18 pages)
3.DSPIC30F3010-30ISO.pdf
(6 pages)
4.DSPIC30F3010-30ISO.pdf
(16 pages)
5.DSPIC30F3010-30ISO.pdf
(22 pages)
6.DSPIC30F3010-20ISP.pdf
(226 pages)
Specifications of DSPIC30F3011-20I/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
30
Program Memory Size
24KB (8K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
30
Flash Memory Size
24KB
Supply Voltage Range
2.5V To 5.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F301120IML
- DSPIC30F3010-30ISO PDF datasheet
- DSPIC30F3010-30ISO PDF datasheet #2
- DSPIC30F3010-30ISO PDF datasheet #3
- DSPIC30F3010-30ISO PDF datasheet #4
- DSPIC30F3010-30ISO PDF datasheet #5
- DSPIC30F3010-20ISP PDF datasheet #6
- Current page: 134 of 228
- Download datasheet (4Mb)
dsPIC30F3010/3011
19.8
The analog input model of the 10-bit ADC is shown in
Figure
function of the internal amplifier settling time, device
V
For the ADC to meet its specified accuracy, the Charge
Holding Capacitor (C
charge to the voltage level on the analog input pin. The
Source Impedance (R
(R
Impedance combine to directly affect the time required
to charge the capacitor, C
impedance of the analog sources must therefore be
small enough to fully charge the holding capacitor
within the chosen sample time. To minimize the effects
of pin leakage currents on the accuracy of the A/D
converter,
impedance, R
is selected (changed), this sampling function must be
completed prior to starting the conversion. The internal
holding capacitor will be in a discharged state prior to
each sample operation.
FIGURE 19-3:
DS70141F-page 134
DD
IC
) and the Internal Sampling Switch (R
and the holding capacitor charge time.
Note:
19-3. The total sampling time for the ADC is a
A/D Acquisition Requirements
the
S
, is 5 kΩ. After the analog input channel
C
PIN
Legend: C
maximum
VA
value depends on device package and is not tested. Effect of C
Rs
HOLD
S
ADC ANALOG INPUT MODEL
), the Interconnect Impedance
V
I
R
R
C
LEAKAGE
ANx
PIN
T
IC
SS
HOLD
) must be allowed to fully
C
PIN
recommended
HOLD
= Input Capacitance
= Threshold Voltage
= Leakage Current at the pin due to
= Interconnect Resistance
= Sampling Switch Resistance
= Sample/Hold Capacitance (from DAC)
various junctions
. The combined
V
DD
V
V
T
T
source
= 0.6V
= 0.6V
SS
)
R
I
± 500 nA
LEAKAGE
IC
≤ 250Ω
The user must allow at least 1 T
time, T
sample to be acquired. This sample time may be
controlled manually in software by setting/clearing the
SAMP bit, or it may be automatically controlled by the
ADC. In an automatic configuration, the user must
allow enough time between conversion triggers so that
the minimum sample time can be satisfied. Refer to the
Section 23.0 “Electrical Characteristics”
sample time requirements.
SAMP
Sampling
Switch
R
SS
, between conversions to allow each
PIN
negligible if Rs ≤ 5 kΩ.
R
SS
V
SS
C
= DAC capacitance
= 4.4 pF
≤ 3 kΩ
HOLD
© 2010 Microchip Technology Inc.
AD
period of sampling
for T
AD
and
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