DSPIC30F3011-20I/ML Microchip Technology, DSPIC30F3011-20I/ML Datasheet - Page 56
![IC DSPIC MCU/DSP 24K 44QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
DSPIC30F3011-20I/ML
Manufacturer Part Number
DSPIC30F3011-20I/ML
Description
IC DSPIC MCU/DSP 24K 44QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F3010-30ISO.pdf
(228 pages)
2.DSPIC30F3010-30ISO.pdf
(18 pages)
3.DSPIC30F3010-30ISO.pdf
(6 pages)
4.DSPIC30F3010-30ISO.pdf
(16 pages)
5.DSPIC30F3010-30ISO.pdf
(22 pages)
6.DSPIC30F3010-20ISP.pdf
(226 pages)
Specifications of DSPIC30F3011-20I/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
30
Program Memory Size
24KB (8K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
30
Flash Memory Size
24KB
Supply Voltage Range
2.5V To 5.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F301120IML
- DSPIC30F3010-30ISO PDF datasheet
- DSPIC30F3010-30ISO PDF datasheet #2
- DSPIC30F3010-30ISO PDF datasheet #3
- DSPIC30F3010-30ISO PDF datasheet #4
- DSPIC30F3010-30ISO PDF datasheet #5
- DSPIC30F3010-20ISP PDF datasheet #6
- Current page: 56 of 226
- Download datasheet (4Mb)
dsPIC30F3010/3011
7.2
7.2.1
In order to erase a block of data EEPROM, the
NVMADRU and NVMADR registers must initially
point to the block of memory to be erased. Configure
NVMCON for erasing a block of data EEPROM, and
set the ERASE and WREN bits in the NVMCON reg-
ister. Setting the WR bit initiates the erase, as shown
in Example 7-2.
EXAMPLE 7-2:
7.2.2
The TBLPAG and NVMADR registers must point to
the block. Select erase a block of data Flash, and set
the ERASE and WREN bits in the NVMCON register.
Setting the WR bit initiates the erase, as shown in
Example 7-3.
EXAMPLE 7-3:
DS70141E-page 54
; Select data EEPROM block, ERASE, WREN bits
; Start erase cycle by setting WR after writing key sequence
; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle
; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete
; Select data EEPROM word, ERASE, WREN bits
; Start erase cycle by setting WR after writing key sequence
; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle
; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete
MOV
MOV
DISI
MOV
MOV
MOV
MOV
BSET
NOP
NOP
MOV
MOV
DISI
MOV
MOV
MOV
MOV
BSET
NOP
NOP
Erasing Data EEPROM
ERASING A BLOCK OF DATA
EEPROM
ERASING A WORD OF DATA
EEPROM
#0x4045,W0
W0
#5
#0x55,W0
W0
#0xAA,W1
W1
NVMCON,#WR
#0x4044,W0
W0
#5
#0x55,W0
W0
#0xAA,W1
W1
NVMCON,#WR
,
,
,
,
,
,
NVMCON
NVMKEY
NVMKEY
NVMCON
NVMKEY
NVMKEY
DATA EEPROM BLOCK ERASE
DATA EEPROM WORD ERASE
;
; Write the 0x55 key
;
; Write the 0xAA key
; Initiate erase sequence
; Initialize NVMCON SFR
; Block all interrupts with priority <7
; for next 5 instructions
;
; Write the 0x55 key
;
; Write the 0xAA key
; Initiate erase sequence
; Block all interrupts with priority <7
; for next 5 instructions
© 2008 Microchip Technology Inc.
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