DSPIC30F3012-30I/P Microchip Technology, DSPIC30F3012-30I/P Datasheet - Page 6

• Manufacturer Part Number: DSPIC30F3012-30I/P
• Description: IC DSPIC MCU/DSP 24K 18DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3012-30I/P

• Program Memory Type: FLASH
• Program Memory Size: 24KB (8K x 24)
• Package / Case: 18-DIP (0.300", 7.62mm)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 12
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC30F005 - MODULE SCKT DSPIC30F 18DIP/SOICDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLEACICE0202 - ADAPTER MPLABICE 18P 300 MIL
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F3012-30IP

dsPIC30F3012/3013
4. Module: CPU
EXAMPLE 4:
5. Module: Interrupt Controller
DS80448D-page 6
LOOP1: MOV
LOOP0: MOV
Note:
...
When using two DO loops in a nested fashion,
terminating the inner-level DO loop by setting the
EDT bit (CORCON<11>) will produce unexpected
results. Specifically, the device may continue
executing code within the outer DO loop forever.
This erratum does not affect the operation of the
MPLAB C30 compiler.
Work around
The application should save the DCOUNT SFR
prior to entering the inner DO loop and restore it
upon exiting the inner DO loop. This work around is
shown in Example 4.
Affected Silicon Revisions
The following sequence of events will lead to an
address
“Interrupt 1” is used to represent any enabled
dsPIC30F interrupt.
1. User software performs one of the following
B0
X
operations:
-
-
-
-
.include “p30fxxxx.inc”
.......
DO
....
PUSH COUNT
DO
BTSS Flag, #0
BSET CORCON, #EDT ;Terminate inner
....
....
POP
For details on the functionality of
EDT bit, see section 2.9.2.4 in the
dsPIC30F Family Reference Manual.
CPU IPL is raised to Interrupt 1 IPL
level or higher, or
Interrupt 1 IPL is lowered to CPU IPL
level or lower, or
Interrupt 1 is disabled (Interrupt 1 IE
bit set to ‘0’), or
Interrupt 1 flag is cleared
B1
....
X
error
#CNT1, LOOP0 ;Outer loop start
#CNT2, LOOP1 ;Inner loop
W1, W5
DCOUNT
W5, W8
SAVE AND RESTORE
DCOUNT
trap.
The
;Save DCOUNT
;starts
;DO-loop early
;Inner loop ends
;Restore DCOUNT
;Outer loop ends
generic
term
EXAMPLE 5:
EXAMPLE 6:
.include "p30fxxxx.inc"
...
DISI #4 ; protect the disable
; of INT1
BCLR IEC1, #INT1IE ; disable interrupt 1
... ; next instruction
;protected by DISI
// Note: Macro defined in device include
// files
#define SET_CPU_IPL (ipl){ \
int DISI_save; \
\
DISI_save = DISICNT; \
asm volatile ("disi #0x3FFF");\
SRbits.IPL = ipl; \
__builtin_nop();
__builtin_nop();
DISICNT = DISI_save; } (void) 0;
#include "p30fxxxx.h"
. . .
SET_CPU_IPL (3)
. . .
2. Interrupt 1 occurs between 2 and 4 instruction
Work arounds
Work around 1: For Assembly Language
Source Code
The user may disable interrupt nesting, disable
interrupts before modifying the Interrupt 1 set-
ting or execute a DISI instruction before modi-
fying the CPU IPL or Interrupt 1. A minimum
DISI value of 4 is required if the DISI instruction
is executed immediately before the CPU IPL or
Interrupt 1 is modified, as shown in Example 5.
It is necessary to have DISI active for four cycles
after the CPU IPL or Interrupt 1 is modified.
Work around 2: For C Language Source Code
For applications using the C language, MPLAB
C30 versions 1.32 and higher provide several
macros for modifying the CPU IPL. The
SET_CPU_IPL macro provides the ability to
safely modify the CPU IPL, as shown in
Example 6.
There is one level of DISI, so this macro saves
and restores the DISI state. For temporarily
modifying and restoring the CPU IPL, the mac-
ros
RESTORE_CPU_IPL can be used, as shown in
Example 7. These macros also make use of the
SET_CPU_IPL macro.
cycles after any of the operations listed above.
SET_AND_SAVE_CPU_IPL
USING DISI
USING SET_CPU_IPL
MACRO
\
\
© 2010 Microchip Technology Inc.
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