DSPIC30F3012-30I/P Microchip Technology, DSPIC30F3012-30I/P Datasheet - Page 2

IC DSPIC MCU/DSP 24K 18DIP

DSPIC30F3012-30I/P

Manufacturer Part Number
DSPIC30F3012-30I/P
Description
IC DSPIC MCU/DSP 24K 18DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr

Specifications of DSPIC30F3012-30I/P

Program Memory Type
FLASH
Program Memory Size
24KB (8K x 24)
Package / Case
18-DIP (0.300", 7.62mm)
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
30 MHz
Number Of Programmable I/os
12
Data Ram Size
2 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC30F005 - MODULE SCKT DSPIC30F 18DIP/SOICDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLEACICE0202 - ADAPTER MPLABICE 18P 300 MIL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
DSPIC30F3012-30IP

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dsPIC30F3012/3013
TABLE 2:
DS80448D-page 2
Operations
Operations
Note 1:
Controller
Compare
Compare
Interrupt
Module
Output
Output
Sleep
Mode
Timer
I
CPU
CPU
CPU
CPU
ADC
PSV
PSV
2
PLL
PLL
I
I/O
C™
2
C
Only those issues indicated in the last column apply to the current silicon revision.
Modification
Sleep Mode
Slave Mode
Sleep Mode
PWM Mode
Lock Status
Instructions
Multiplexed
Addressing
Instruction
Nested DO
Instruction
MAC Class
Address
Feature
Port Pin
with IC1
SILICON ISSUE SUMMARY
with ±4
DAW.b
Loops
10-bit
DISI
bit
Number
Item
12.
10.
11.
13.
14.
15.
16.
17.
1.
2.
3.
4.
5.
6.
7.
8.
9.
Sequential MAC instructions, which prefetch data from Y data
space using ±4 address modification will cause an address error
trap.
The Decimal Adjust instruction, DAW.b, may improperly clear the
Carry bit, C (SR<0>).
In certain instructions, fetching one of the operands from
program memory using Program Space Visibility (PSV) will
corrupt specific bits in the STATUS Register, SR.
When using two DO loops in a nested fashion, terminating the
inner-level DO loop by setting the EDT bit (CORCON<11>) will
produce unexpected results.
An interrupt occurring immediately after modifying the CPU IPL,
interrupt IPL, interrupt enable, or interrupt flag may cause an
address error trap.
The DISI instruction will not disable interrupts if a DISI
instruction is executed in the same instruction cycle that the
DISI counter decrements to zero.
Output compare will produce a glitch when loading 0% duty
cycle in PWM mode. It will also miss the next compare after the
glitch.
The output compare module will produce a glitch on the output
when an I/O pin is initially set high and the module is configured
to drive the pin low at a specified time.
ADC event triggers from the INT0 pin will not wake-up the device
from Sleep mode if the SMPI bits are non-zero.
If 4x or 8x PLL mode is used, the input frequency range is 5 MHz-
10 MHz instead of 4 MHz-10 MHz.
Execution of the Sleep instruction (PWRSAV #0) may cause
incorrect program operation after the device wakes up from
Sleep. The current consumption during Sleep may also increase
beyond the specifications listed in the device data sheet.
The I
I
The Port I/O pin multiplexed with the Input Capture 1 (IC1)
function cannot be used as a digital input pin when the UART
auto-baud feature is enabled.
When the I
the same address bits (A10 and A9) as other I
A10 and A9 bits may not work as expected.
Clock switching prevents the device from waking up from Sleep.
The PLL LOCK Status bit (OSCCON<5>) can occasionally get
cleared and generate an oscillator failure trap even when the
PLL is still locked and functioning correctly.
An address error trap occurs in certain addressing modes when
accessing the first four bytes of any PSV page.
2
C slave.
2
C module loses incoming data bytes when operating as an
2
C module is configured for 10-bit addressing using
Issue Summary
2
C devices, the
© 2010 Microchip Technology Inc.
Revisions
B0
Affected
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
B1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(1)

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