PIC18F67J90-I/PT Microchip Technology, PIC18F67J90-I/PT Datasheet - Page 49

• Manufacturer Part Number: PIC18F67J90-I/PT
• Description: IC PIC MCU FLASH 128KB 64-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F67J90-I/PT

• Core Size: 8-Bit
• Program Memory Size: 128KB (64K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 51
• Ram Memory Size: 3.8310546875KB
• Cpu Speed: 48MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3923 B
• Interface Type: AUSART, EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Operating Supply Voltage: 2.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

4.0
The PIC18F87J90 family of devices differentiates
between various kinds of Reset:
• Power-on Reset (POR)
• MCLR Reset during normal operation
• MCLR Reset during power-managed modes
• Watchdog Timer (WDT) Reset (during
• Brown-out Reset (BOR)
• Configuration Mismatch (CM)
• RESET Instruction
• Stack Full Reset
• Stack Underflow Reset
This section discusses Resets generated by MCLR,
POR and BOR and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 5.1.4.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in Section 24.2 “Watchdog
Timer (WDT)”.
FIGURE 4-1:
© 2009 Microchip Technology Inc.
execution)
Note 1: The ENVREG pin must be tied high to enable Brown-out Reset. The Brown-out Reset is provided by the on-chip
MCLR
V
DD
Configuration Word
RESET
PWRT
32 μs (typical)
Instruction
Mismatch
RESET
voltage regulator when there is insufficient source voltage to maintain regulation.
Pointer
Stack
INTRC
Brown-out
V
Time-out
Reset
Detect
DD
IDLE
Sleep
WDT
Rise
Stack Full/Underflow Reset
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
(1)
External Reset
POR Pulse
PWRT
11-Bit Ripple Counter
65.5 ms (typical)
Preliminary
PIC18F87J90 FAMILY
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 4-1.
4.1
Device Reset events are tracked through the RCON
register (Register 4-1). The lower five bits of the
register indicate that a specific Reset event has
occurred. In most cases, these bits can only be set by
the event and must be cleared by the application after
the event. The state of these flag bits, taken together,
can be read to indicate the type of Reset that just
occurred. This is described in more detail in
Section 4.7 “Reset State of Registers”.
The RCON register also has a control bit for setting
interrupt priority (IPEN). Interrupt priority is discussed
in Section 8.0 “Interrupts”.
RCON Register
S
R
DS39933C-page 47
Q
Chip_Reset