PIC18F67J90-I/PT Microchip Technology, PIC18F67J90-I/PT Datasheet - Page 431

• Manufacturer Part Number: PIC18F67J90-I/PT
• Description: IC PIC MCU FLASH 128KB 64-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F67J90-I/PT

• Core Size: 8-Bit
• Program Memory Size: 128KB (64K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 51
• Ram Memory Size: 3.8310546875KB
• Cpu Speed: 48MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3923 B
• Interface Type: AUSART, EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Operating Supply Voltage: 2.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

INDEX
A
A/D .................................................................................... 283
Absolute Maximum Ratings .............................................. 387
AC (Timing) Characteristics .............................................. 402
ACKSTAT ......................................................................... 239
ACKSTAT Status Flag ...................................................... 239
ADCAL Bit ......................................................................... 291
ADCON0 Register............................................................. 283
ADCON1 Register............................................................. 283
ADCON2 Register............................................................. 283
ADDFSR ........................................................................... 376
ADDLW ............................................................................. 339
Addressable Universal Synchronous Asynchronous
ADDULNK ......................................................................... 376
ADDWF ............................................................................. 339
ADDWFC .......................................................................... 340
ADRESH Register............................................................. 283
ADRESL Register ..................................................... 283, 286
Analog-to-Digital Converter. See A/D.
ANDLW ............................................................................. 340
ANDWF ............................................................................. 341
Assembler
AUSART
© 2009 Microchip Technology Inc.
A/D Converter Interrupt, Configuring ........................ 287
Acquisition Requirements ......................................... 288
ADCAL Bit................................................................. 291
ADCON0 Register..................................................... 283
ADCON1 Register..................................................... 283
ADCON2 Register..................................................... 283
ADRESH Register............................................. 283, 286
ADRESL Register ..................................................... 283
Analog Port Pins, Configuring................................... 289
Associated Registers ................................................ 291
Automatic Selecting and Configuring
Configuring the Module............................................. 287
Conversion Clock (T
Conversion Requirements ........................................ 420
Conversion Status (GO/DONE Bit) ........................... 286
Conversions .............................................................. 290
Converter Calibration ................................................ 291
Converter Characteristics ......................................... 419
Operation in Power-Managed Modes ....................... 291
Special Event Trigger (CCP)..................................... 290
Use of the CCP2 Trigger........................................... 290
Load Conditions for Device Timing Specifications.... 403
Parameter Symbology .............................................. 402
Temperature and Voltage Specifications .................. 403
Timing Conditions ..................................................... 403
GO/DONE Bit............................................................ 286
Receiver Transmitter (AUSART). See AUSART.
MPASM Assembler................................................... 384
Asynchronous Mode ................................................. 274
Baud Rate Generator (BRG)..................................... 272
Acquisition Time ............................................... 289
Associated Registers, Receive ......................... 277
Associated Registers, Transmit ........................ 275
Receiver............................................................ 276
Setting up 9-Bit Mode with Address Detect ...... 276
Transmitter........................................................ 274
Associated Registers ........................................ 272
Baud Rate Error, Calculating ............................ 272
Baud Rates, Asynchronous Modes .................. 273
High Baud Rate Select (BRGH Bit) .................. 272
AD
) ............................................ 289
Preliminary
PIC18F87J90 FAMILY
B
Baud Rate Generator ....................................................... 235
BC..................................................................................... 341
BCF .................................................................................. 342
BF ..................................................................................... 239
BF Status Flag .................................................................. 239
Bias Generation (LCD)
Block Diagrams
Synchronous Master Mode....................................... 278
Synchronous Slave Mode......................................... 281
Charge Pump Design Considerations ...................... 187
A/D............................................................................ 286
Analog Input Model................................................... 287
AUSART Receive ..................................................... 276
AUSART Transmit .................................................... 274
Baud Rate Generator ............................................... 235
Capture Mode Operation .......................................... 170
Comparator Analog Input Model............................... 297
Comparator I/O Operating Modes ............................ 294
Comparator Output................................................... 296
Comparator Voltage Reference................................ 300
Comparator Voltage Reference Output Buffer
Compare Mode Operation ........................................ 171
Connections for On-Chip Voltage Regulator ............ 328
CTMU ....................................................................... 303
CTMU Current Source Calibration Circuit ................ 306
CTMU Typical Connections and Internal
CTMU Typical Connections and Internal
Device Clock............................................................... 29
EUSART Receive ..................................................... 260
EUSART Transmit .................................................... 258
External Power-on Reset Circuit (Slow V
Fail-Safe Clock Monitor ............................................ 330
Generic I/O Port Operation....................................... 111
Interrupt Logic............................................................. 96
LCD Clock Generation.............................................. 182
LCD Driver Module ................................................... 177
LCD Regulator Connections (M0 and M1) ............... 184
MSSP (I
MSSP (I
MSSP (SPI Mode) .................................................... 205
On-Chip Reset Circuit................................................. 47
PIC18F6XJ90 ............................................................. 10
PIC18F8XJ90 ............................................................. 11
PLL ............................................................................. 34
PWM Operation (Simplified) ..................................... 173
Reads From Flash Program Memory ......................... 87
Resistor Ladder Connections for
Operation in Power-Managed Modes............... 272
Sampling .......................................................... 272
Associated Registers, Receive......................... 280
Associated Registers, Transmit........................ 279
Reception ......................................................... 280
Transmission .................................................... 278
Associated Registers, Receive......................... 282
Associated Registers, Transmit........................ 281
Reception ......................................................... 282
Transmission .................................................... 281
Example ........................................................... 301
Configuration for Pulse Delay Generation ........ 314
Configuration for Time Measurement ............... 313
Power-up) ........................................................... 49
Configuration M2 .............................................. 185
2
2
C Master Mode)......................................... 233
C Mode)..................................................... 214
DS39933C-page 429
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