ATMEGA16A-PU Atmel, ATMEGA16A-PU Datasheet - Page 164
Manufacturer Part Number
MCU AVR 16K FLASH 16MHZ 40-PDIP
1.ATMEGA16A-MU.pdf (352 pages)
2.ATMEGA16A-MU.pdf (19 pages)
Specifications of ATMEGA16A-PU
I²C, SPI, UART/USART
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
Program Memory Size
16KB (8K x 16)
Program Memory Type
512 x 8
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Data Bus Width
Data Ram Size
Maximum Clock Frequency
Number Of Programmable I/os
Number Of Timers
Maximum Operating Temperature
+ 85 C
3rd Party Development Tools
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
8-ch x 10-bit
Operating Supply Voltage
No. Of I/o's
Eeprom Memory Size
Ram Memory Size
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
19.10 Accessing UBRRH/ UCSRC Registers
If the receiver is set up to receive frames that contain 5 to 8 data bits, then the first stop bit indi-
cates if the frame contains data or address information. If the receiver is set up for frames with
nine data bits, then the ninth bit (RXB8) is used for identifying address and data frames. When
the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the
frame type bit is zero the frame is a data frame.
The Multi-processor Communication mode enables several Slave MCUs to receive data from a
Master MCU. This is done by first decoding an address frame to find out which MCU has been
addressed. If a particular Slave MCU has been addressed, it will receive the following data
frames as normal, while the other Slave MCUs will ignore the received frames until another
address frame is received.
For an MCU to act as a Master MCU, it can use a 9-bit character frame format (UCSZ = 7). The
ninth bit (TXB8) must be set when an address frame (TXB8 = 1) or cleared when a data frame
(TXB = 0) is being transmitted. The Slave MCUs must in this case be set to use a 9-bit character
The following procedure should be used to exchange data in Multi-processor Communication
Using any of the 5- to 8-bit character frame formats is possible, but impractical since the receiver
must change between using n and n+1 character frame formats. This makes full-duplex opera-
tion difficult since the transmitter and receiver uses the same character size setting. If 5- to 8-bit
character frames are used, the transmitter must be set to use two stop bit (USBS = 1) since the
first stop bit is used for indicating the frame type.
Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCM bit. The
MPCM bit shares the same I/O location as the TXC Flag and this might accidentally be cleared
when using SBI or CBI instructions.
The UBRRH Register shares the same I/O location as the UCSRC Register. Therefore some
special consideration must be taken when accessing this I/O location.
When doing a write access of this I/O location, the high bit of the value written, the USART Reg-
ister Select (URSEL) bit, controls which one of the two registers that will be written. If URSEL is
zero during a write operation, the UBRRH value will be updated. If URSEL is one, the UCSRC
setting will be updated.
1. All Slave MCUs are in Multi-processor Communication mode (MPCM in UCSRA is set).
2. The Master MCU sends an address frame, and all Slaves receive and read this frame.
3. Each Slave MCU reads the UDR Register and determines if it has been selected. If so,
4. The addressed MCU will receive all data frames until a new address frame is received.
5. When the last data frame is received by the addressed MCU, the addressed MCU sets
In the Slave MCUs, the RXC Flag in UCSRA will be set as normal.
it clears the MPCM bit in UCSRA, otherwise it waits for the next address byte and
keeps the MPCM setting.
The other Slave MCUs, which still have the MPCM bit set, will ignore the data frames.
the MPCM bit and waits for a new address frame from Master. The process then
repeats from 2.