DSPIC33FJ32MC202-I/MM Microchip Technology, DSPIC33FJ32MC202-I/MM Datasheet - Page 381

IC DSPIC MCU/DSP 32K 28QFN

DSPIC33FJ32MC202-I/MM

Manufacturer Part Number
DSPIC33FJ32MC202-I/MM
Description
IC DSPIC MCU/DSP 32K 28QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr

Specifications of DSPIC33FJ32MC202-I/MM

Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-QFN
Core Frequency
40MHz
Core Supply Voltage
2.75V
Embedded Interface Type
I2C, JTAG, SPI, UART
No. Of I/o's
21
Flash Memory Size
32KB
Supply Voltage Range
3V To 3.6V
Package
28QFN-S EP
Device Core
dsPIC
Family Name
dSPIC33
Maximum Speed
40 MHz
Operating Supply Voltage
3.3 V
Data Bus Width
16 Bit
Number Of Programmable I/os
21
Interface Type
I2C/SPI/UART
On-chip Adc
6-chx10-bit|6-chx12-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164336 - MODULE SOCKET FOR PM3 28/44QFNDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC33FJ32MC202-I/MM
Manufacturer:
Microchip
Quantity:
1 485
Part Number:
DSPIC33FJ32MC202-I/MM
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
TABLE 31-40: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)
© 2011 Microchip Technology Inc.
AC CHARACTERISTICS
IM10
IM11
IM20
IM21
IM25
IM26
IM30
IM31
IM33
IM34
IM40
IM45
IM50
IM51
Note 1:
Param
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
No.
2:
3:
T
T
T
T
T
T
T
T
T
T
T
T
C
T
Symbol
SU
SU
SU
AA
R
LO
HI
F
HD
HD
HD
BF
PGD
B
BRG is the value of the I
(I
site for the latest dsPIC33F/PIC24H Family Reference Manual sections.
Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
Typical value for this parameter is 130 ns.
:
:
2
:
SCL
SCL
:
:
:
:
:
:
SCL
:
:
:
C™)” (DS70195) in the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web
DAT
STA
STO
SCL
SCL
SDA
DAT
STA
STO
Clock Low Time 100 kHz mode
Clock High Time 100 kHz mode
SDAx and SCLx
Fall Time
SDAx and SCLx
Rise Time
Data Input
Setup Time
Data Input
Hold Time
Start Condition
Setup Time
Start Condition
Hold Time
Stop Condition
Setup Time
Stop Condition
Hold Time
Output Valid
From Clock
Bus Free Time
Bus Capacitive Loading
Pulse Gobbler Delay
Characteristic
2
C Baud Rate Generator. Refer to Section 19. “Inter-Integrated Circuit™
400 kHz mode
1 MHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
100 kHz mode
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
CY
CY
CY
CY
CY
CY
CY
CY
CY
CY
CY
CY
CY
CY
CY
CY
CY
CY
20 + 0.1 C
20 + 0.1 C
/2 (BRG + 1)
/2 (BRG + 1)
/2 (BRG + 1)
/2 (BRG + 1)
/2 (BRG + 1)
/2 (BRG + 1)
/2 (BRG + 1)
/2 (BRG + 1)
/2 (BRG + 1)
/2 (BRG + 1)
/2 (BRG + 1)
/2 (BRG + 1)
/2 (BRG + 1)
/2 (BRG + 1)
/2 (BRG + 1)
/2 (BRG + 1)
/2 (BRG + 1)
/2 (BRG + 1)
Min
250
100
0.2
4.7
1.3
0.5
40
65
0
0
(1)
B
B
1000
3500
1000
Max
300
300
100
300
300
400
390
0.9
400
-40°C ≤ T
-40°C ≤ T
Units
pF
μs
μs
μs
μs
μs
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
ns
ns
ns
ns
ns
μs
μs
μs
ns
A
A
≤ +85°C for Industrial
≤ +125°C for Extended
C
from 10 to 400 pF
C
from 10 to 400 pF
Only relevant for
Repeated Start
condition
After this period the
first clock pulse is
generated
Time the bus must be
free before a new
transmission can start
B
B
is specified to be
is specified to be
DS70291E-page 381
Conditions
See Note 3

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