DSPIC33FJ32MC202-I/MM Microchip Technology, DSPIC33FJ32MC202-I/MM Datasheet - Page 139

• Manufacturer Part Number: DSPIC33FJ32MC202-I/MM
• Description: IC DSPIC MCU/DSP 32K 28QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ32MC202-I/MM

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-QFN
• Core Frequency: 40MHz
• Core Supply Voltage: 2.75V
• Embedded Interface Type: I2C, JTAG, SPI, UART
• No. Of I/o's: 21
• Flash Memory Size: 32KB
• Supply Voltage Range: 3V To 3.6V
• Package: 28QFN-S EP
• Device Core: dsPIC
• Family Name: dSPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 6-chx10-bit|6-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164336 - MODULE SOCKET FOR PM3 28/44QFNDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REGISTER 8-5:
REGISTER 8-6:
© 2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
Note 1:
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-10
bit 9-0
Note 1:
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
R/W-0
R/W-0
R/W-0
U-0
—
2:
If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the
DMA channel and should be avoided.
If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the
DMA channel and should be avoided.
Number of DMA transfers = CNT<9:0> + 1.
PAD<15:0>: Peripheral Address Register bits
Unimplemented: Read as ‘0’
CNT<9:0>: DMA Transfer Count Register bits
R/W-0
R/W-0
R/W-0
U-0
—
DMAxPAD: DMA CHANNEL x PERIPHERAL ADDRESS REGISTER
DMAxCNT: DMA CHANNEL x TRANSFER COUNT REGISTER
‘1’ = Bit is set
‘1’ = Bit is set
W = Writable bit
W = Writable bit
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
U-0
—
CNT<7:0>
PAD<15:8>
PAD<7:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(2)
R/W-0
R/W-0
R/W-0
(2)
U-0
—
R/W-0
R/W-0
R/W-0
U-0
—
x = Bit is unknown
x = Bit is unknown
R/W-0
R/W-0
R/W-0
R/W-0
(1)
CNT<9:8>
DS70291E-page 139
(1)
R/W-0
R/W-0
R/W-0
(2)
R/W-0
bit 8
bit 0
bit 8
bit 0