DSPIC30F2010-20I/MM Microchip Technology, DSPIC30F2010-20I/MM Datasheet - Page 5

• Manufacturer Part Number: DSPIC30F2010-20I/MM
• Description: IC DSPIC MCU/DSP 12K 28QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2010-20I/MM

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-QFN
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 12KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F2010-20I/MMG; DSPIC30F201020IMM; DSPIC30F201020IMM

5. Module: Early Termination of Nested DO
EXAMPLE 6:
© 2008 Microchip Technology Inc.
LOOP1: MOV
LOOP0:
Note:
When using two DO loops in a nested fashion,
terminating the inner-level DO loop by setting the
EDT (CORCON<11>) bit will produce unexpected
results. Specifically, the device may continue
executing code within the outer DO loop forever.
This erratum does not affect the operation of the
MPLAB C30 compiler.
Work around
The application should save the DCOUNT SFR
prior to entering the inner DO loop and restore it
upon exiting the inner DO loop. This work around is
shown in Example 6.
.include “p30fxxxx.inc”
.......
DO #CNT1, LOOP0
....
PUSH
DO
....
BTSS
BSET
....
....
POP
...
For details on the functionality of
EDT bit, see section 2.9.2.4
in the dsPIC30F Family Reference
Manual.
MOV
Loops
DCOUNT
#CNT2, LOOP1
Flag, #0
CORCON, #EDT;Terminate inner
W1, W5
DCOUNT
W5, W8
SAVE AND RESTORE
DCOUNT
;Outer loop start
;Save DCOUNT
;starts
;DO-loop early
;Inner loop ends
;Restore DCOUNT
;Outer loop ends
;Inner loop
6. Module: Interrupting a
EXAMPLE 7:
EXAMPLE 8:
__T1Interrupt:
__T1Interrupt:
When interrupt nesting is enabled (or NSTDIS
(INTCON1<15>) bit is ‘0’), the following sequence
of events will lead to an address error trap:
1. REPEAT loop is active.
2. An interrupt is generated during the execution
3. The CPU executes the Interrupt Service
4. Within the ISR, when the CPU is executing the
Work around
Processing of Interrupt Service Routines should
be disabled while the RETFIE instruction is being
executed. This may be accomplished in two
different ways:
1. Place a DISI instruction immediately before
2. Immediately prior to executing the RETFIE
PUSH
.......
BCLR
POP
DISI
RETFIE
PUSH
.......
BCLR
MOV.B
MOV.B
POP
RETFIE
of the REPEAT loop.
Routine (ISR) of the source causing the
interrupt.
first instruction cycle of the 3-cycle RETFIE
(Return from Interrupt) instruction, a second
interrupt is generated by a source with a higher
interrupt priority.
the RETFIE instruction in all Interrupt Service
Routines of interrupt sources that may be
interrupted by other higher priority interrupt
sources (with priority levels 1 through 6). This
is shown in Example 7 in the Timer1 ISR. In
this example, a DISI instruction inhibits level 1
through level 6 interrupts for 2 instruction
cycles, while the RETFIE instruction is
executed.
instruction, increase the CPU priority level by
modifying the IPL<2:0> (SR<7:5>) bits to ‘111’
as shown in Example 8. This will disable all
interrupts between priority levels 1 through 7.
W0
IFS0, #T1IF
W0
#1
W0
IFS0, #T1IF
#0xE0, W0
WREG, SR
W0
dsPIC30F2010
;Another interrupt occurs
;here and it is processed
;correctly
;Another interrupt occurs
;here and it is processed
;correctly
DISI BEFORE RETFIE
RAISE IPL BEFORE RETFIE
;Timer1 ISR
;This line optional
;This line optional
;Timer1 ISR
REPEAT
DS80186J-page 5
Loop