DSPIC30F2010-20I/MM Microchip Technology, DSPIC30F2010-20I/MM Datasheet - Page 2

• Manufacturer Part Number: DSPIC30F2010-20I/MM
• Description: IC DSPIC MCU/DSP 12K 28QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2010-20I/MM

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-QFN
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 20
• Flash Memory Size: 12KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F2010-20I/MMG; DSPIC30F201020IMM; DSPIC30F201020IMM

dsPIC30F2010
14. 4x PLL Operation
15. Interrupt Controller – Sequential Interrupts
16. 8x PLL Mode
17. SPI Module
18. Quadrature Encoder Interface (QEI) Module
19. Sleep Mode
20. I
21. Motor Control PWM – PWM Counter Register
22. I/O Port – Port Pin Multiplexed with IC1
DS80186J-page 2
The 4x PLL mode of operation may not function
correctly for certain input frequencies.
Sequential interrupts after modifying the CPU IPL,
interrupt IPL, interrupt enable or interrupt flag may
cause an address error trap.
If 8x PLL mode is used, the input frequency range
is 5-10 MHz instead of 4-10 MHz.
When enabled, the SPI module does not disable
RF2 as general I/O.
The QEI module does not generate an interrupt in
a particular overflow condition.
Execution of the Sleep instruction (PWRSAV #0)
may cause incorrect program operation after the
device wakes up from Sleep. The current
consumption during Sleep may also increase
beyond the specifications listed in the device data
sheet.
The I
operating as an I
PTMR does not continue counting down after
halting code execution in Debug mode.
The Port I/O pin multiplexed with the Input Capture
1 (IC1) function cannot be used as a digital input
pin when the UART auto-baud feature is enabled.
2
C™ Module
2
C module loses incoming data bytes when
2
C slave.
23. FRC
24. I
25. Timer Module
26. PLL Lock Status Bit
27. PSV Operations
28. I
29. I
30. I
The following sections describe the errata and work
around to these errata, where they may apply.
Internal FRC accuracy does not perform to
specification.
When the I
addressing using the same address bits (A10 and
A9) as other I
not work as expected.
Clock switching prevents the device from waking
up from Sleep.
The PLL LOCK Status bit (OSCCON<5>) can
occasionally get cleared and generate an
oscillator failure trap even when the PLL is still
locked and functioning correctly.
An address error trap occurs in certain addressing
modes when accessing the first four bytes of any
PSV page.
The 10-bit slave does not set the RBF flag or load
the I2CxRCV register on address match if the
Least Significant bits of the address are the same
as the 7-bit reserved addresses.
When the I
slave with an address of 0x102, the I2CxRCV
register content for the lower address byte is 0x01
rather than 0x02.
When the I
device generates a glitch on the SDA and SCL
pins, causing a false communication start in a
single-master configuration or a bus collision in a
multi-master configuration.
2
2
2
2
C Module: 10-bit Addressing Mode
C Module: 10-bit Addressing Mode
C Module: 10-bit Addressing Mode
C Module
2
2
C module is enabled, the dsPIC
2
C module is configured as a 10-bit
2
C module is configured for 10-bit
C devices, the A10 and A9 bits may
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