ATMEGA8515L-8PU Atmel, ATMEGA8515L-8PU Datasheet - Page 204

• Manufacturer Part Number: ATMEGA8515L-8PU
• Description: IC AVR MCU 8K 8MHZ 3V 40DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8515L-8PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: ATMEGA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 8MHz
• Total Internal Ram Size: 512Byte
• # I/os (max): 35
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 40
• Package Type: PDIP W
• Controller Family/series: AVR MEGA
• No. Of I/o's: 35
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 8MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

204
ATmega8515(L)
Figure 91. External Memory Timing (SRWn1 = 1, SRWn0 = 0)
Figure 92. External Memory Timing (SRWn1 = 1, SRWn0 = 1)
Note:
System Clock (CLK
System Clock (CLK
DA7:0 (XMBK = 0)
DA7:0 (XMBK = 0)
1. The ALE pulse in the last period (T4-T7) is only present if the next instruction
A15:8
DA7:0
CPU
ALE
DA7:0
WR
A15:8
RD
CPU
ALE
accesses the RAM (internal or external).
WR
)
RD
)
Prev. Addr.
Prev. Data
Prev. Addr.
Prev. Data
T1
T1
1
Address
Address
4
2
1
5
T2
6
Address
Address
3a
3b
4
2
XX
7
5
8
T2
6
13
3a
3b
XX
10
7
8
13
T3
10
T3
Address
Data
12
Data
16
15
T4
9
Address
Data
12
Data
16
15
9
T4
T5
11
(1)
T5
T6
11
14
2512F–AVR–12/03
T6
14
T7