PIC18LF24J11-I/SS Microchip Technology, PIC18LF24J11-I/SS Datasheet - Page 308

IC PIC MCU FLASH 16K 2V 28-SSOP

PIC18LF24J11-I/SS

Manufacturer Part Number
PIC18LF24J11-I/SS
Description
IC PIC MCU FLASH 16K 2V 28-SSOP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets

Specifications of PIC18LF24J11-I/SS

Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
28-SSOP
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
EUSART, I2C, SPI
Maximum Clock Frequency
31 KHz
Number Of Programmable I/os
16
Number Of Timers
5
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DM183022, DM183033, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
suspended, leaving the SDAx line held low and the Start
PIC18F46J11 FAMILY
18.5.7.2
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
deasserts the SCLx pin (SCLx allowed to float high).
When the SCLx pin is allowed to float high, the BRG is
suspended from counting until the SCLx pin is actually
FIGURE 18-20:
18.5.8
To initiate a Start condition, the user sets the Start
Enable bit, SEN (SSPxCON2<0>). If the SDAx and
SCLx pins are sampled high, the BRG is reloaded with
the contents of SSPxADD<6:0> and starts its count. If
SCLx and SDAx are both sampled high when the Baud
Rate Generator times out (T
driven low. The action of the SDAx being driven low
while SCLx is high is the Start condition and causes the
Start bit (SSPxSTAT<3>) to be set. Following this, the
BRG is reloaded with the contents of SSPxADD<6:0>
and resumes its count. When the BRG times out
(T
automatically cleared by hardware. The BRG is
condition is complete.
FIGURE 18-21:
DS39932C-page 308
BRG
), the SEN bit (SSPxCON2<0>) will be
I
CONDITION TIMING
2
Clock Arbitration
C MASTER MODE START
SDAx
SCLx
BRG
Value
BRG
Reload
Write to SEN bit occurs here
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
FIRST START BIT TIMING
SDAx
SCLx
03h
BRG
DX
), the SDAx pin is
SCLx deasserted but slave holds
SCLx low (clock arbitration)
02h
SCLx is sampled high, reload takes
place and BRG starts its count
SDAx = 1,
SCLx = 1
T
BRG
01h
Set S bit (SSPxSTAT<3>)
T
S
BRG
BRG decrements on
Q2 and Q4 cycles
00h (hold off)
At completion of Start bit,
hardware clears SEN bit
sampled high. When the SCLx pin is sampled high, the
BRG is reloaded with the contents of SSPxADD<6:0>
and begins counting. This ensures that the SCLx high
time will always be at least one BRG rollover count in
the event that the clock is held low by an external
device (Figure 18-20).
18.5.8.1
If the user writes the SSPxBUF when a Start sequence
is in progress, the WCOL bit is set and the contents of
the buffer are unchanged (the write does not occur).
and sets SSPxIF bit
Note:
Note:
DX – 1
Write to SSPxBUF occurs here
T
BRG
1st bit
If, at the beginning of the Start condition, the
SDAx and SCLx pins are already sampled
low or if during the Start condition, the SCLx
line is sampled low, before the SDAx line is
driven low, a bus collision occurs, the Bus
Collision Interrupt Flag, BCLxIF, is set, the
Start condition is aborted and the I
module is reset into its Idle state.
Because queueing of events is not
allowed, writing to the lower five bits of
SSPxCON2 is disabled until the Start
condition is complete.
WCOL Status Flag
SCLx allowed to transition high
T
BRG
03h
© 2009 Microchip Technology Inc.
02h
2nd bit
2
C

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