ATTINY48-PU Atmel, ATTINY48-PU Datasheet - Page 58
ATTINY48-PU
Manufacturer Part Number
ATTINY48-PU
Description
MCU AVR 4K ISP FLASH 1.8V 28-DIP
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY48-PU
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Processor Series
ATTINY4x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
2-Wire/I2S/SPI
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
28
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
6-ch x 10-bit
Package
28PDIP
Device Core
AVR
Family Name
ATtiny
Maximum Speed
12 MHz
Operating Supply Voltage
2.5|3.3|5 V
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY48-PU
Manufacturer:
ATMEL
Quantity:
5 530
Company:
Part Number:
ATTINY48-PU
Manufacturer:
AVX
Quantity:
30 000
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9.3.5
9.3.6
58
ATtiny48/88
PCIFR – Pin Change Interrupt Flag Register
PCMSK3 – Pin Change Mask Register 3
• Bits 7:4 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 3 – PCIF3: Pin Change Interrupt Flag 3
When a logic change on any PCINT[27:24] pin triggers an interrupt request, PCIF3 becomes set
(one). If the I-bit in SREG and the PCIE3 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
• Bit 2 – PCIF2: Pin Change Interrupt Flag 2
When a logic change on any PCINT[23:16] pin triggers an interrupt request, PCIF2 becomes set
(one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
• Bit 1 – PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT[15:8] pin triggers an interrupt request, PCIF1 becomes set
(one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
• Bit 0 – PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT[7:0] pin triggers an interrupt request, PCIF0 becomes set
(one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
• Bits 7:4 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bits 3:0 – PCINT[27:24]: Pin Change Enable Mask 27:24
Each PCINT[27:24] bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT[27:24] is set and the PCIE3 bit in PCICR is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT[27:24] is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
Bit
0x1B (0x3B)
Read/Write
Initial Value
Bit
(0x6A)
Read/Write
Initial Value
R
7
–
0
R
7
–
0
R
6
–
0
R
6
–
0
5
–
R
0
R
5
–
0
R
4
–
0
R
4
–
0
PCINT27
R/W
PCIF3
R/W
3
0
3
0
PCINT26
PCIF2
R/W
R/W
2
0
2
0
PCINT25
PCIF1
R/W
R/W
1
0
1
0
PCINT24
PCIF0
R/W
R/W
0
0
0
0
8008G–AVR–04/11
PCMSK3
PCIFR
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