ATTINY48-PU Atmel, ATTINY48-PU Datasheet - Page 120
![MCU AVR 4K ISP FLASH 1.8V 28-DIP](/photos/7/21/72189/453-28-dip_sml.jpg)
ATTINY48-PU
Manufacturer Part Number
ATTINY48-PU
Description
MCU AVR 4K ISP FLASH 1.8V 28-DIP
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY48-PU
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Processor Series
ATTINY4x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
2-Wire/I2S/SPI
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
28
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
6-ch x 10-bit
Package
28PDIP
Device Core
AVR
Family Name
ATtiny
Maximum Speed
12 MHz
Operating Supply Voltage
2.5|3.3|5 V
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY48-PU
Manufacturer:
ATMEL
Quantity:
5 530
Company:
Part Number:
ATTINY48-PU
Manufacturer:
AVX
Quantity:
30 000
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14. SPI – Serial Peripheral Interface
14.1
14.2
120
Features
Overview
ATtiny48/88
•
•
•
•
•
•
•
•
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the
ATtiny48/88 and peripheral devices or between several AVR devices.
Figure 14-1. SPI Block Diagram
Note:
Full-duplex, Three-wire Synchronous Data Transfer
Master or Slave Operation
LSB First or MSB First Data Transfer
Seven Programmable Bit Rates
End of Transmission Interrupt Flag
Write Collision Flag Protection
Wake-up from Idle Mode
Double Speed (CK/2) Master SPI Mode
/2/4/8/16/32/64/128
1. Refer to
SPI STATUS REGISTER
DIVIDER
SELECT
XTAL
SPI CONTROL
Figure 1-1 on page
SPI CLOCK (MASTER)
SPI INTERRUPT
REQUEST
(1)
MSTR
SPE
2, and
8
MSB
INTERNAL
DATA BUS
8
8 BIT SHIFT REGISTER
Table 10-5 on page 69
READ DATA BUFFER
8
SPI CONTROL REGISTER
CLOCK
LOGIC
CLOCK
LSB
for SPI pin placement.
M
M
M
S
S
S
8008G–AVR–04/11
MISO
MOSI
SCK
SS
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