ATTINY48-PU Atmel, ATTINY48-PU Datasheet - Page 136
![MCU AVR 4K ISP FLASH 1.8V 28-DIP](/photos/7/21/72189/453-28-dip_sml.jpg)
ATTINY48-PU
Manufacturer Part Number
ATTINY48-PU
Description
MCU AVR 4K ISP FLASH 1.8V 28-DIP
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY48-PU
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Processor Series
ATTINY4x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
2-Wire/I2S/SPI
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
28
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
6-ch x 10-bit
Package
28PDIP
Device Core
AVR
Family Name
ATtiny
Maximum Speed
12 MHz
Operating Supply Voltage
2.5|3.3|5 V
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY48-PU
Manufacturer:
ATMEL
Quantity:
5 530
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Part Number:
ATTINY48-PU
Manufacturer:
AVX
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15.6.3
15.6.4
136
ATtiny48/88
Bus Interface Unit
Address Match Unit
The TWI can be set to operate in high-speed mode, as described in
Register” on page
mode it relies on a prescaled version of the same. Depending on the clock signal used, the SCL
frequency is generated according to one of the following equations.
In normal mode:
In high-speed mode:
...where:
Note:
This unit contains the Data and Address Shift Register (TWDR), a START/STOP Controller and
Arbitration detection hardware. The TWDR contains the address or data bytes to be transmitted,
or the address or data bytes received. In addition to the 8-bit TWDR, the Bus Interface Unit also
contains a register containing the (N)ACK bit to be transmitted or received. This (N)ACK Regis-
ter is not directly accessible by the application software. However, when receiving, it can be set
or cleared by manipulating the TWI Control Register (TWCR). When in Transmitter mode, the
value of the received (N)ACK bit can be determined by the value in the TWSR.
The START/STOP Controller is responsible for generation and detection of START, REPEATED
START, and STOP conditions. The START/STOP controller is able to detect START and STOP
conditions even when the AVR MCU is in one of the sleep modes, enabling the MCU to wake up
if addressed by a Master.
If the TWI has initiated a transmission as Master, the Arbitration Detection hardware continu-
ously monitors the transmission trying to determine if arbitration is in process. If the TWI has lost
an arbitration, the Control Unit is informed. Correct action can then be taken and appropriate
status codes generated.
The Address Match unit checks if received address bytes match the seven-bit address in the
TWI Address Register (TWAR). If the TWI General Call Recognition Enable (TWGCE) bit in the
TWAR is written to one, all incoming address bits will also be compared against the General Call
address. Upon an address match, the Control Unit is informed, allowing correct action to be
taken. The TWI may or may not acknowledge its address, depending on settings in the TWCR.
The Address Match unit is able to compare addresses even when the AVR MCU is in sleep
• clk
• clk
• TWBR = value of TWI Bit Rate Register, see
• TWPS = value of TWI prescaler, see
I/O
TWIHS
In TWI Master mode TWBR must be 10, or higher .
= prescaled system clock, see
= system clock, see
160. In high-speed mode the TWI uses the system clock, whereas in normal
f
f
SCL
SCL
Figure 6-1 on page 28
=
=
--------------------------------------------------------------------
16
--------------------------------------------------------------------
16
Figure 6-1 on page 28
Table 15-7 on page 159
+
+
(
(
2
2
×
×
clk
TWBR
TWBR
“TWBR – TWI Bit Rate Register” on page 156
clk
TWIHS
I/O
×
×
TWPS
TWPS
)
)
“TWHSR – TWI High Speed
8008G–AVR–04/11
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