ATTINY2313V-10PU Atmel, ATTINY2313V-10PU Datasheet - Page 57

• Manufacturer Part Number: ATTINY2313V-10PU
• Description: IC MCU AVR 2K FLASH 20DIP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY2313V-10PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: ATTINY2x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SPI/UART/USI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Package: 20PDIP
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 10 MHz
• Data Rom Size: 128 B
• Height: 4.95 mm
• Length: 26.92 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Width: 7.11 mm
• For Use With: ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2543L–AVR–08/10
Table 29
Figure 25 on page
Table 29. Overriding Signals for Alternate Functions PD7..PD4
Table 30. Overriding Signals for Alternate Functions in PD3..PD0
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
and
PD6/ICP
0
0
0
0
0
0
0
ICP ENABLE
1
ICP INPUT
–
PD3/INT1
0
0
0
0
0
0
0
INT1 ENABLE
1
INT1 INPUT
–
Table 30
51.
relates the alternate functions of Port D to the overriding signals shown in
PD2/INT0/XCK/
CKOUT
0
0
0
0
XCKO_PVOE
XCKO_PVOV
0
INT0 ENABLE/
XCK INPUT
ENABLE
1
INT0 INPUT/
XCK INPUT
–
PD5/OC1B/T1
0
0
0
0
OC1B_PVOE
OC1B_PVOV
0
T1 ENABLE
1
T1 INPUT
–
PD1/TXD
TXD_OE
0
TXD_OE
1
TXD_OE
TXD_PVOV
0
0
0
–
–
PD4/T0
0
0
0
0
0
0
0
T0 ENABLE
1
T0 INPUT
AIN1
PD0/RXD
RXD_OE
PORTD0 • PUD
RXD_EN
0
0
0
0
0
0
RXD INPUT
–
57