ATTINY2313V-10PU Atmel, ATTINY2313V-10PU Datasheet - Page 139

• Manufacturer Part Number: ATTINY2313V-10PU
• Description: IC MCU AVR 2K FLASH 20DIP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY2313V-10PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: ATTINY2x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SPI/UART/USI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Package: 20PDIP
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 10 MHz
• Data Rom Size: 128 B
• Height: 4.95 mm
• Length: 26.92 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Width: 7.11 mm
• For Use With: ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Functional
Descriptions
Three-wire Mode
2543L–AVR–08/10
The Two-wire clock control unit can generate an interrupt when a start condition is detected on
the Two-wire bus. It can also generate wait states by holding the clock pin low after a start con-
dition is detected, or after the counter overflows.
The USI Three-wire mode is compliant to the Serial Peripheral Interface (SPI) mode 0 and 1, but
does not have the slave select (SS) pin functionality. However, this feature can be implemented
in software if necessary. Pin names used by this mode are: DI, DO, and USCK.
Figure 61. Three-wire Mode Operation, Simplified Diagram
Figure 61
The two Shift Registers are interconnected in such way that after eight USCK clocks, the data in
each register are interchanged. The same clock also increments the USI’s 4-bit counter. The
Counter Overflow (interrupt) Flag, or USIOIF, can therefore be used to determine when a trans-
fer is completed. The clock is generated by the Master device software by toggling the USCK pin
via the PORT Register or by writing a one to the USITC bit in USICR.
Figure 62. Three-wire Mode, Timing Diagram
CYCLE
USCK
USCK
SLAVE
MASTER
DO
DI
shows two USI units operating in Three-wire mode, one as Master and one as Slave.
Bit7
Bit7
( Reference )
Bit6
Bit6
A
Bit5
Bit5
B
MSB
Bit4
Bit4
MSB
C
1
Bit3
Bit3
D
Bit2
Bit2
2
6
6
Bit1
Bit1
Bit0
Bit0
3
5
5
4
4
4
5
3
3
PORTxn
6
2
2
USCK
USCK
DO
DO
DI
DI
7
1
1
LSB
LSB
8
E
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