ATTINY2313V-10PU Atmel, ATTINY2313V-10PU Datasheet - Page 118

• Manufacturer Part Number: ATTINY2313V-10PU
• Description: IC MCU AVR 2K FLASH 20DIP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY2313V-10PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: ATTINY2x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SPI/UART/USI
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Package: 20PDIP
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 10 MHz
• Data Rom Size: 128 B
• Height: 4.95 mm
• Length: 26.92 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Width: 7.11 mm
• For Use With: ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Data Transmission
– The USART
Transmitter
Sending Frames with
5 to 8 Data Bit
118
ATtiny2313
The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRB
Register. When the Transmitter is enabled, the normal port operation of the TxD pin is overrid-
den by the USART and given the function as the Transmitter’s serial output. The baud rate,
mode of operation and frame format must be set up once before doing any transmissions. If syn-
chronous operation is used, the clock on the XCK pin will be overridden and used as
transmission clock.
A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The
CPU can load the transmit buffer by writing to the UDR I/O location. The buffered data in the
transmit buffer will be moved to the Shift Register when the Shift Register is ready to send a new
frame. The Shift Register is loaded with new data if it is in idle state (no ongoing transmission) or
immediately after the last stop bit of the previous frame is transmitted. When the Shift Register is
loaded with new data, it will transfer one complete frame at the rate given by the Baud Register,
U2X bit or by XCK depending on mode of operation.
The following code examples show a simple USART transmit function based on polling of the
Data Register Empty (UDRE) flag. When using frames with less than eight bits, the most signifi-
cant bits written to the UDR are ignored. The USART has to be initialized before the function can
be used. For the assembly code, the data to be sent is assumed to be stored in Register R16
Note:
The function simply waits for the transmit buffer to be empty by checking the UDRE flag, before
loading it with new data to be transmitted. If the Data Register Empty interrupt is utilized, the
interrupt routine writes the data into the buffer.
Assembly Code Example
C Code Example
USART_Transmit:
void USART_Transmit( unsigned char data )
{
}
; Wait for empty transmit buffer
sbis UCSRA,UDRE
rjmp USART_Transmit
; Put data (r16) into buffer, sends the data
out
ret
/* Wait for empty transmit buffer */
while ( !( UCSRA & (1<<UDRE)) )
/* Put data into buffer, sends the data */
UDR = data;
1. The example code assumes that the part specific header file is included.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”
instructions must be replaced with instructions that allow access to extended I/O. Typically
“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
UDR,r16
;
(1)
(1)
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