ATTINY44A-PU Atmel, ATTINY44A-PU Datasheet - Page 48
![IC MCU AVR 4K FLASH 20MHZ 14PDIP](/photos/7/39/73953/313-14-dip_sml.jpg)
ATTINY44A-PU
Manufacturer Part Number
ATTINY44A-PU
Description
IC MCU AVR 4K FLASH 20MHZ 14PDIP
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY44A-PU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
12
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
14-DIP (0.300", 7.62mm)
Processor Series
ATTINY4x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI/USI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
20-ch x 10-bit
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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9.2
9.2.1
48
External Interrupts
ATtiny24A/44A/84A
Low Level Interrupt
External Interrupts are triggered by the INT0 pin or any of the PCINT[11:0] pins. Observe that, if
enabled, the interrupts will trigger even if the INT0 or PCINT[11:0] pins are configured as out-
puts. This feature provides a way of generating a software interrupt. Pin change 0 interrupts
PCI0 will trigger if any enabled PCINT[7:0] pin toggles. Pin change 1 interrupts PCI1 will trigger
if any enabled PCINT[11:8] pin toggles. The PCMSK0 and PCMSK1 Registers control which
pins contribute to the pin change interrupts. Pin change interrupts on PCINT[11:0] are detected
asynchronously, which means that these interrupts can be used for waking the part also from
sleep modes other than Idle mode.
The INT0 interrupt can be triggered by a falling or rising edge or a low level. This is set up as
shown in
and configured as level triggered, the interrupt will trigger as long as the pin is held low. Note
that recognition of falling or rising edge interrupts on INT0 requires the presence of an I/O clock,
as described in
A low level interrupt on INT0 is detected asynchronously. This means that the interrupt source
can be used for waking the part also from sleep modes other than Idle (the I/O clock is halted in
all sleep modes except Idle).
Address Labels Code
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
0x000A
0x000B
0x000C
0x000D
0x000E
0x000F
0x0010
;
0x0011
0x0012
0x0013
0x0014
0x0015
0x0016
...
“MCUCR – MCU Control Register” on page
RESET: ldi
“Clock Sources” on page
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
out
ldi
out
sei
<instr>
...
RESET
INT0
PCINT0
PCINT1
WDT
TIM1_CAPT
TIM1_COMPA
TIM1_COMPB
TIM1_OVF
TIM0_COMPA
TIM0_COMPB
TIM0_OVF
ANA_COMP
ADC
EE_RDY
USI_STR
USI_OVF
r16, high(RAMEND); Main program start
SPH,r16
r16, low(RAMEND)
SPL,r16
25.
Comments
; Reset Handler
; IRQ0 Handler
; PCINT0 Handler
; PCINT1 Handler
; Watchdog Interrupt Handler
; Timer1 Capture Handler
; Timer1 Compare A Handler
; Timer1 Compare B Handler
; Timer1 Overflow Handler
; Timer0 Compare A Handler
; Timer0 Compare B Handler
; Timer0 Overflow Handler
; Analog Comparator Handler
; ADC Conversion Handler
; EEPROM Ready Handler
; USI STart Handler
; USI Overflow Handler
; Set Stack Pointer to top of RAM
; Enable interrupts
50. When the INT0 interrupt is enabled
8183C–AVR–03/11
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