ATTINY44A-PU Atmel, ATTINY44A-PU Datasheet - Page 101
![IC MCU AVR 4K FLASH 20MHZ 14PDIP](/photos/7/39/73953/313-14-dip_sml.jpg)
ATTINY44A-PU
Manufacturer Part Number
ATTINY44A-PU
Description
IC MCU AVR 4K FLASH 20MHZ 14PDIP
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY44A-PU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
12
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
14-DIP (0.300", 7.62mm)
Processor Series
ATTINY4x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI/USI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
20-ch x 10-bit
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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12.9
8183C–AVR–03/11
Timer/Counter Timing Diagrams
Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using
ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However,
if the base PWM frequency is actively changed by changing the TOP value, using the OCR1A as
TOP is clearly a better choice due to its double buffer feature.
In phase and frequency correct PWM mode, the compare units allow generation of PWM wave-
forms on the OC1x pins. Setting the COM1x[1:0] bits to two will produce a non-inverted PWM
and an inverted PWM output can be generated by setting the COM1x[1:0] to three (See
12-4 on page
for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or
clearing) the OC1x Register at the compare match between OCR1x and TCNT1 when the coun-
ter increments, and clearing (or setting) the OC1x Register at compare match between OCR1x
and TCNT1 when the counter decrements. The PWM frequency for the output when using
phase and frequency correct PWM can be calculated by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x Register represents special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the
output will be continuously low and if set equal to TOP the output will be set to high for non-
inverted PWM mode. For inverted PWM the output will have the opposite logic values.
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when interrupt
flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for
modes utilizing double buffering).
Figure 12-10. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling
Figure 12-11 on page 102
TCNTn
OCRnx
OCFnx
(clk
clk
clk
I/O
I/O
Tn
/1)
107). The actual OC1x value will only be visible on the port pin if the data direction
OCRnx - 1
shows the same timing data, but with the prescaler enabled.
f
OCnxPFCPWM
Figure 12-10
OCRnx
OCRnx Value
shows a timing diagram for the setting of OCF1x.
=
--------------------------- -
2 N TOP
⋅
f
clk_I/O
⋅
ATtiny24A/44A/84A
OCRnx + 1
T1
) is therefore shown as a
OCRnx + 2
Table
101
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