ATTINY44A-PU Atmel, ATTINY44A-PU Datasheet - Page 145
![IC MCU AVR 4K FLASH 20MHZ 14PDIP](/photos/7/39/73953/313-14-dip_sml.jpg)
ATTINY44A-PU
Manufacturer Part Number
ATTINY44A-PU
Description
IC MCU AVR 4K FLASH 20MHZ 14PDIP
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY44A-PU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
12
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
14-DIP (0.300", 7.62mm)
Processor Series
ATTINY4x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI/USI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
20-ch x 10-bit
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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8183C–AVR–03/11
done by first turning off the ADC, then changing multiplexer settings and then turn on the ADC.
Alternatively, the first conversion results after changing multiplexer settings should be discarded.
Table 16-4.
Notes:
See
tions of offset calibration channels. MUX0 bit works as a gain selection bit for differential
channels. When MUX0 is cleared (‘0’) 1x gain is selected and when it is set (‘1’) 20x gain is
selected. For normal differential channel pairs MUX5 bit work as a polarity reversal bit. Toggling
of the MUX5 bit exhanges the positive and negative channel other way a round.
Table 16-5.
Single Ended Input
ADC0 (PA0)
ADC1 (PA1)
ADC2 (PA2)
ADC3 (PA3)
ADC4 (PA4)
ADC5 (PA5)
ADC6 (PA6)
ADC7 (PA7)
Reserved for differential channels
0V (AGND)
1.1V (I Ref)
ADC8
Reserved for offset calibration
Reserved for reversal differential channels
Positive Differential Input
ADC0 (PA0)
ADC1 (PA1)
Table 16-5
(3)
1. See
2. After switching to internal voltage reference the ADC requires a settling time of 1ms before
3. See
4. For offset calibration, only. See
measurements are stable. Conversions starting before this may not be reliable. The ADC must
be enabled during the settling time.
(2)
Single-Ended Input channel Selections
Differential Input channel Selections.
Table 16-5
“Temperature Measurement” on page
for details of selections of differential input channel selections as well as selec-
for details.
(4)
(1)
Negative Differential Input
ADC0 (PA0)
ADC1 (PA1)
ADC3 (PA3)
ADC0 (PA0)
ADC2 (PA2)
ADC3 (PA3)
(1)
Table 16-5 on page 145
(1)
143.
ATtiny24A/44A/84A
and
“Operation” on page
Gain 1x
001000
001010
101000
001100
001110
N/A
001000 - 011111
100011 - 100111
101000 - 111111
MUX[5:0]
MUX[5:0]
000000
000001
000010
000011
000100
000101
000110
000111
100000
100001
100010
Gain 20x
100011
001001
001011
101001
001101
001111
133.
145
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