PIC18F23K20-I/MV Microchip Technology, PIC18F23K20-I/MV Datasheet - Page 233

• Manufacturer Part Number: PIC18F23K20-I/MV
• Description: IC MCU 8BIT 8KB FLASH 28UQFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F23K20-I/MV

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 28-UFQFN Exposed Pad
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 768 B
• Interface Type: MSSP, I2C, SPI, USART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• A/d Bit Size: 10 bit
• A/d Channels Available: 10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

17.4.17.3
Bus collision occurs during a Stop condition if:
a)
b)
FIGURE 17-31:
FIGURE 17-32:
 2010 Microchip Technology Inc.
After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
After the SCL pin is deasserted, SCL is sampled
low before SDA goes high.
SDA
SCL
PEN
BCLIF
P
SSPIF
SDA
SCL
PEN
BCLIF
P
SSPIF
Bus Collision During a Stop
Condition
BUS COLLISION DURING A STOP CONDITION (CASE 1)
BUS COLLISION DURING A STOP CONDITION (CASE 2)
SDA asserted low
Assert SDA
T
BRG
T
BRG
T
BRG
T
BRG
The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSPADD<7:0>
and counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’ (Figure 17-31). If the SCL pin is
sampled low before SDA is allowed to float high, a bus
collision occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 17-32).
PIC18F2XK20/4XK20
SCL goes low before SDA goes high,
set BCLIF
T
BRG
T
BRG
SDA sampled
low after T
set BCLIF
‘0’
‘0’
DS41303G-page 233
‘0’
‘0’
BRG
,