PIC18F23K20-I/MV Microchip Technology, PIC18F23K20-I/MV Datasheet - Page 143

• Manufacturer Part Number: PIC18F23K20-I/MV
• Description: IC MCU 8BIT 8KB FLASH 28UQFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F23K20-I/MV

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 28-UFQFN Exposed Pad
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 768 B
• Interface Type: MSSP, I2C, SPI, USART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• A/d Bit Size: 10 bit
• A/d Channels Available: 10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

11.0
PIC18F2XK20/4XK20
Capture/Compare/PWM)
contains a 16-bit register which can operate as a 16-bit
Capture register, a 16-bit Compare register or a PWM
Master/Slave Duty Cycle register.
CCP1 is implemented as an enhanced CCP module with
standard Capture and Compare modes and enhanced
PWM modes. The ECCP implementation is discussed in
Section 16.0
(ECCP) Module”. CCP2 is implemented as a standard
CCP module without the enhanced features.
REGISTER 11-1:
 2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5-4
bit 3-0
U-0
—
CAPTURE/COMPARE/PWM
(CCP) MODULES
“Enhanced
Unimplemented: Read as ‘0’
DC2B<1:0>: PWM Duty Cycle bit 1 and bit 0 for CCP2 Module
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbs
(DC2B<9:2>) of the duty cycle are found in CCPR2L.
CCP2M<3:0>: CCP2 Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCP2 module)
0001 = Reserved
0010 = Compare mode, toggle output on match (CCP2IF bit is set)
0011 = Reserved
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode: initialize CCP2 pin low; on compare match, force CCP2 pin high
1001 = Compare mode: initialize CCP2 pin high; on compare match, force CCP2 pin low
1010 = Compare mode: generate software interrupt on compare match (CCP2IF bit is set,
1011 = Compare mode: trigger special event, reset timer, start A/D conversion on
11xx = PWM mode
U-0
—
CCP2CON: STANDARD CAPTURE/COMPARE/PWM CONTROL REGISTER
devices
(CCP2IF bit is set)
(CCP2IF bit is set)
CCP2 pin reflects I/O state)
CCP2 match (CCP2IF bit is set)
modules.
Capture/Compare/PWM
W = Writable bit
‘1’ = Bit is set
DC2B1
R/W-0
have
Each
two
module
DC2B0
R/W-0
CCP
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CCP2M3
R/W-0
The Capture and Compare operations described in this
chapter apply to both standard and enhanced CCP
modules.
PIC18F2XK20/4XK20
Note: Throughout this section and Section 16.0
“Enhanced Capture/Compare/PWM (ECCP)
Module”, references to the register and bit
names for CCP modules are referred to
generically by the use of ‘x’ or ‘y’ in place of the
specific module number. Thus, “CCPxCON”
might refer to the control register for CCP1,
CCP2 or ECCP1. “CCPxCON” is used
throughout these sections to refer to the
module control register, regardless of whether
the CCP module is a standard or enhanced
implementation.
CCP2M2
R/W-0
x = Bit is unknown
CCP2M1
R/W-0
DS41303G-page 143
CCP2M0
R/W-0
bit 0