PIC18F24J10-I/SO Microchip Technology, PIC18F24J10-I/SO Datasheet - Page 200
![IC PIC MCU FLASH 8KX16 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC18F24J10-I/SO
Manufacturer Part Number
PIC18F24J10-I/SO
Description
IC PIC MCU FLASH 8KX16 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F24J10-ISO.pdf
(368 pages)
3.PIC18F24J10-ISO.pdf
(6 pages)
4.PIC18F24J10-ISO.pdf
(6 pages)
5.PIC18F24J10-ISO.pdf
(12 pages)
6.PIC18F44J10-IPT.pdf
(358 pages)
Specifications of PIC18F24J10-I/SO
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1024 B
Interface Type
SPI, I2C, MSSP, USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 100 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28P
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- PIC16F616T-ISL PDF datasheet
- PIC18F24J10-ISO PDF datasheet #2
- PIC18F24J10-ISO PDF datasheet #3
- PIC18F24J10-ISO PDF datasheet #4
- PIC18F24J10-ISO PDF datasheet #5
- PIC18F44J10-IPT PDF datasheet #6
- Current page: 200 of 368
- Download datasheet (6Mb)
PIC18F45J10 FAMILY
EXAMPLE 17-1:
TABLE 17-2:
DS39682E-page 198
TXSTA
RCSTA
BAUDCON ABDOVF
SPBRGH
SPBRG
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
For a device with F
Desired Baud Rate
Solving for SPBRGH:SPBRG:
Calculated Baud Rate
Error
Name
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
CSRC
SPEN
Bit 7
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
X
OSC
CALCULATING BAUD RATE ERROR
of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:
= F
= ((F
= ((16000000/9600)/64) – 1
= [25.042] = 25
= 16000000/(64 (25 + 1))
= 9615
= (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
= (9615 – 9600)/9600 = 0.16%
RCIDL
Bit 6
RX9
TX9
OSC
OSC
/(64 ([SPBRGH:SPBRG] + 1))
/Desired Baud Rate)/64) – 1
TXEN
SREN
Bit 5
—
SYNC
CREN
SCKP
Bit 4
SENDB
ADDEN
BRG16
Bit 3
BRGH
FERR
Bit 2
—
OERR
TRMT
WUE
Bit 1
© 2009 Microchip Technology Inc.
ABDEN
RX9D
TX9D
Bit 0
Reset Values
on page
49
49
49
49
49
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