PIC18F24J10-I/SO Microchip Technology, PIC18F24J10-I/SO Datasheet - Page 129

• Manufacturer Part Number: PIC18F24J10-I/SO
• Description: IC PIC MCU FLASH 8KX16 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F24J10-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1024 B
• Interface Type: SPI, I2C, MSSP, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28P
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

14.0
PIC18F45J10 family devices all have two CCP
(Capture/Compare/PWM) modules. Each module
contains a 16-bit register which can operate as a 16-bit
Capture register, a 16-bit Compare register or a PWM
Master/Slave Duty Cycle register.
In 28-pin devices, the two standard CCP modules
(CCP1 and CCP2) operate as described in this chapter.
In 40/44-pin devices, CCP1 is implemented as an
Enhanced CCP module (ECCP1) with standard Capture
and Compare modes and Enhanced PWM modes. The
Enhanced CCP implementation is discussed in
Section 15.0
(ECCP) Module”.
REGISTER 14-1:
© 2009 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5-4
bit 3-0
U-0
—
CAPTURE/COMPARE/PWM
(CCP) MODULES
“Enhanced
Unimplemented: Read as ‘0’
DCxB<1:0>: PWM Duty Cycle bit 1 and bit 0
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbs (DCxB<9:2>)
of the duty cycle are found in CCPRxL.
CCPxM<3:0>: CCPx Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCPx module)
0001 = Reserved
0010 = Compare mode, toggle output on match (CCPxIF bit is set)
0011 = Reserved
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode: initialize CCPx pin low; on compare match, force CCPx pin high
1001 = Compare mode: initialize CCPx pin high; on compare match, force CCPx pin low
1010 = Compare mode: generate software interrupt on compare match (CCPxIF bit is set,
1011 = Compare mode: trigger special event, reset timer, start A/D conversion on
11xx = PWM mode
U-0
—
CCPxCON: CCP1/CCP2 CONTROL REGISTER IN 28-PIN DEVICES
(CCPxIF bit is set)
(CCPxIF bit is set)
CCPx pin reflects I/O state)
CCPx match (CCPxIF bit is set)
Capture/Compare/PWM
W = Writable bit
‘1’ = Bit is set
DCxB1
R/W-0
DCxB0
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F45J10 FAMILY
CCPxM3
R/W-0
The Capture and Compare operations described in this
chapter apply to all standard and Enhanced CCP
modules.
Note: Throughout this section and Section 15.0
“Enhanced Capture/Compare/PWM (ECCP)
Module”, references to the register and bit
names for CCP modules are referred to gener-
ically by the use of ‘x’ or ‘y’ in place of the
specific module number. Thus, “CCPxCON”
might refer to the control register for CCP1,
CCP2 or ECCP1. “CCPxCON” is used
throughout these sections to refer to the
module control register regardless of whether
the CCP module is a standard or Enhanced
implementation.
CCPxM2
R/W-0
x = Bit is unknown
CCPxM1
R/W-0
DS39682E-page 127
CCPxM0
R/W-0
bit 0