PESD5V0V4UF,115 NXP Semiconductors, PESD5V0V4UF,115 Datasheet - Page 9

DIODE ESD PROTECT VLOW 6-XSON

PESD5V0V4UF,115

Manufacturer Part Number
PESD5V0V4UF,115
Description
DIODE ESD PROTECT VLOW 6-XSON
Manufacturer
NXP Semiconductors
Series
-r
Datasheet

Specifications of PESD5V0V4UF,115

Package / Case
6-XSON (Micropak™), SOT-886
Voltage - Reverse Standoff (typ)
5V
Voltage - Breakdown
6.4V
Power (watts)
16W
Polarization
4 Channel Array - Unidirectional
Mounting Type
Surface Mount
Polarity
Unidirectional
Channels
4 Channels
Clamping Voltage
13 V
Operating Voltage
5 V
Breakdown Voltage
6.8 V
Peak Surge Current
1.5 A
Peak Pulse Power Dissipation
16 W
Capacitance
12 pF
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 65 C
Dimensions
1.05(Max) mm W x 1.5(Max) mm L
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-4804-2
934061202115
PESD5V0V4UF T/R
PESD5V0V4UF T/R
PESD5V0V4UF,115
NXP Semiconductors
7. Application information
PESDXV4UF_G_W_3
Product data sheet
The devices are designed for the protection of up to four unidirectional data or signal lines
from the damage caused by ESD and surge pulses. The devices may be used on lines
where the signal polarities are both, positive and negative with respect to ground. The
devices provide a surge capability of 16 W per line for an 8/20 s waveform each.
Circuit board layout and protection device placement
Circuit board layout is critical for the suppression of ESD, Electrical Fast Transient (EFT)
and surge transients. The following guidelines are recommended:
1. Place the device as close to the input terminal or connector as possible.
2. The path length between the device and the protected line should be minimized.
3. Keep parallel signal paths to a minimum.
4. Avoid running protected conductors in parallel with unprotected conductors.
5. Minimize all Printed-Circuit Board (PCB) conductive loops including power and
6. Minimize the length of the transient return path to ground.
7. Avoid using shared transient return paths to a common ground point.
8. Ground planes should be used whenever possible. For multilayer PCBs, use ground
Fig 9. Application diagram
ground loops.
vias.
unidirectional protection of 4 lines
Rev. 03 — 28 January 2008
Very low capacitance quadruple ESD protection diode arrays
1
2
3
DUT
5
4
bidirectional protection of 3 lines
n.c.
PESDxV4UF/G/W
1
2
3
data- or transmission lines
DUT
006aab126
5
4
© NXP B.V. 2008. All rights reserved.
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