AD7853 Analog Devices, AD7853 Datasheet
AD7853
Specifications of AD7853
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AD7853 Summary of contents
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... The part powers up with a set of default conditions and can operate as a read only ADC. The AD7853 is capable of 200 kHz throughput rate while the AD7853L is capable of 100 kHz throughput rate. The input track-and-hold acquires a signal in 500 ns and features a pseudo- differential sampling scheme ...
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... LOGIC INPUTS Input High Voltage, V INH 2.4 2.1 Input Low Voltage, V INL 0.8 0.6 Input Current Input Capacitance unless otherwise noted.) Specifications in () apply to the AD7853L. A MIN MAX Version Units 71 dB min –78 dB max –78 dB max –80 dB typ –80 dB typ 12 ...
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... The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7853/AD7853L can calibrate. Note also that these are voltage spans and are not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–) and the allowable system full-scale voltage applied between AIN(+) and AIN(– ...
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... Internal DAC Plus System Full-Scale Cal Time, Master Clock Dependent (111114 t 3.47 ms typ System Offset Calibration Time, Master Clock Dependent (13899 t –4– MHz for AD7853 and 1.8/1 MHz for AD7853L; T CLKIN ) CLKIN ) CLKIN ) CLKIN ) and timed from a voltage level of 1.6 V. See ...
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... CONVST signal, the conversion can be initiated in software by writing to the control register. POLARITY PIN LOGIC HIGH t 1 CONVST (I/ BUSY (O/P) SYNC (I/P) SCLK (I/P) DOUT (O/P) Figure 2. AD7853/AD7853L Timing Diagram (Typical Read and Write Operation for Interface Modes 2, 3) POLARITY PIN LOGIC HIGH t 1 CONVST (I/ BUSY (O/P) SYNC (O/P) SCLK (O/ ...
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... AD7853LAN DD + 0.3 V AD7853LBN AD7853AR AD7853BR AD7853LAR AD7853LBR AD7853ARS AD7853LARS EVAL-AD7853CB EVAL-CONTROL BOARD NOTES 1 Linearity error refers to the integral linearity error Plastic DIP SOIC SSOP signifies the low power version. 4 This can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes ...
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... Serial Data Input. The data to be written is applied to this pin in serial form (16-bit word). This pin can act as an input pin I/O pin depending on the serial interface mode the part is in (see Table X). 22 CLKIN Master Clock Signal for the device (4 MHz for AD7853, 1.8 MHz for AD7853L). Sets the conversion and calibration times. 23 SCLK Serial Port Clock ...
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... Signal to (Noise + Distortion) = (6.02 N +1.76) dB Thus for a 12-bit converter, this is 74 dB. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7853/AD7853L defined as: THD (dB) 20 log where V is the rms amplitude of the fundamental and V ...
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... ON-CHIP REGISTERS The AD7853/AD7853L powers up with a set of default conditions, and the user need not ever write to the device. In this case the AD7853/AD7853L will operate as a Read-Only ADC. The AD7853/AD7853L still retains the flexibility for performing a full power- down, and a full self-calibration. Note that the DIN pin should be tied to DGND for operating the AD7853/AD7853L as a Read- Only ADC ...
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... AD7853/AD7853L CONTROL REGISTER The arrangement of the control register is shown below. The control register is a write only register and contains 14 bits of data. The control register is selected by putting two 1s in ADDR1 and ADDR0. The function of the bits in the control register are described below. The power-up status of all bits is 0. ...
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... Registers for more details). REV. B START WRITE TO CONTROL REGISTER SETTING RDSLT0 = RDSLT1 = 1 READ STATUS REGISTER Figure 6. Flowchart for Reading the Status Register ZERO ZERO ZERO 2/3 MODE X CALMD Status Register Bit Function Descriptions –11– AD7853/AD7853L ZERO PMGT1 PMGT0 CALSLT1 CALSLT0 STCAL LSB ...
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... CALIBRATION REGISTERS The AD7853/AD7853L has ten calibration registers in all, eight for the DAC, one for the offset and one for gain. Data can be writ- ten to or read from all ten calibration registers. In self- and system calibration the part automatically modifies the calibration regis- ters ...
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... The maximum analog input range that the gain register can compensate for is 1.025 times the reference voltage, and the minimum input range is 0.975 times the reference voltage. –13– AD7853/AD7853L approximately. REF 13 V )/2 ...
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... CONVST rising edge. However, the maximum throughput rates are achieved by reading/writing during conver- sion, and reading/writing during conversion is likely to degrade the Signal to (Noise + Distortion) by only 0.5 dBs. The AD7853 can operate at throughput rates up to 200 kHz, 100 kHz for the AD7853L. For the AD7853/AD7853L a conversion takes ...
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... TYPICAL CONNECTION DIAGRAM Figure 10 shows a typical connection diagram for the AD7853/ AD7853L. The DIN line is tied to DGND so that no data is written to the part. The AGND and the DGND pins are con- nected together at the device for good noise suppression. The CAL pin has a 0.01 F capacitor to enable an automatic self- calibration on power-up ...
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... V– AD820-3V 10k Figure 13. Analog Input Buffering Input Ranges The analog input range for the AD7853/AD7853L both the unipolar and bipolar ranges. REF The only difference between the unipolar range and the bipolar range is that in the bipolar range the AIN(–) has to be biased up ...
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... F C REF1 0 REF2 0.01 F REF IN 0.1 F Figure 19. Relevant Connections When Using AV Reference REV. B PERFORMANCE CURVES Figure 20 shows a typical FFT plot for the AD7853 at 200 kHz sample rate and 10 kHz input frequency. /REF pin IN OUT pin and a 100 nF OUT –100 0.1 F –120 Figure 21 shows the SNR versus Frequency for different sup- plies and different external references ...
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... PMGT1 and PMGT0 as shown in Table VI, a Full Power-Down, Full Power-Up, Full Power- Down Between Conversions, and a Partial Power-Down Be- tween Conversions can be selected. A typical connection diagram for a low power application is shown in Figure 23 (AD7853L is the low power version of the AD7853). 1.8MHz OSCILLATOR MASTER CLOCK INPUT 0.1 F ...
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... The AD7853 powers up from a full hardware or software power-down typ. This limits the throughput which the part is capable of to 104 kSPS for the AD7853 operating with a 4 MHz CLK and 66 kSPS for the AD7853L with a 1.8 MHz CLK when powering down between conversions. Figure 24 shows how power-down between conversions is implemented using the CONVST pin ...
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... When using this mode of operation, the AD7853 is only powered up for the duration of the conver- sion. If the power-up time of the AD7853 is taken and it is assumed that the current during power- typ, then power consumption as a function of throughput can easily be calculated ...
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... Figure 27. System Calibration Description System calibration allows the user to take out system errors external to the AD7853/AD7853L as well as calibrate the errors of the AD7853/AD7853L itself. The maximum calibration range for the system offset errors system gain errors is 2. ...
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... AD7853/AD7853L System Gain and Offset Interaction The inherent architecture of the AD7853/AD7853L leads to an interaction between the system offset and gain errors when a system calibration is performed. Therefore it is recommended to perform the cycle of a system offset calibration followed by a system gain calibration twice. Separate system offset and system gain calibrations reduce the offset and gain errors to at least the 12-bit level ...
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... Table IX details the five interface modes and the serial clock edges from which the data is clocked out by the AD7853/ AD7853L (DOUT Edge) and that the data is latched in on (DIN Edge). The logic level of the POLARITY pin is shown and it is clear that this reverses the edges. ...
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... AD7853/AD7853L DETAILED TIMING SECTION Mode 1 (2-Wire 8051 Interface) The read and writing takes place on the DIN line and the con- version is initiated by pulsing the CONVST pin (note that in every write cycle the 2/3 Mode bit must be set to 1). The con- version may be started by setting the CONVST bit in the con- trol register to 1 instead of using the CONVST line ...
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... DB15 DB14 DB13 DB12 t 8 DB14 DB13 DB12 DB11 –25– AD7853/AD7853L , before this rising edge. The POLARITY 7 MIN/MAX (CONTINUOUS SCLK MIN/MAX (CONTINUOUS SCLK) (5V/3V) SCLK THREE- DB10 DB0 STATE t 8 DB10 DB0 MIN/MAX (CONTINUOUS SCLK), ...
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... Figure 39. Timing Diagram for Read/Write with SYNC Output and SCLK Output (Continuous and Noncontinuous) (i.e., Operating Mode Numbers 4 and 5, SM1 = 1, SM2 = 1 and 0) data on the DIN pin is also clocked in to the AD7853/AD7853L by the same SCLK for the next conversion. The read/write operations must be complete after sixteen clock cycles (which takes 4 ...
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... TO GO LOW APPLY SYNC (IF REQUIRED), SCLK AND READ CONVERSION RESULT ON DOUT PIN Figure 40. Flowchart for Setting Up and Reading from the AD7853/AD7853L REV this case there is no writing to the on-chip registers and only the conversion result data is read from the part. Interface Mode 1 cannot be used in this case necessary to write to the control register to set Interface Mode 1 ...
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... To enable Serial Interface Mode 1, the user must also write to the part. Figure 41 through 43 outline flowcharts of how to configure the AD7853/AD7853L for each of the differ- ent serial interface modes. The continuous loops on all diagrams indicate the sequence for more than one conversion. The options ...
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... REV. B Interface Modes 4 and 5 Configuration Figure 43 shows the flowchart for configuring the AD7853/ AD7853L in Interface Modes 4 and 5, the self-clocking modes. In this case it is not recommended to use the software conver- sion start option. The read and write operations always occur simultaneously and during conversion. ...
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... MHz/1.8MHz MASTER Figure 46 shows the AD7853/AD7853L SPI/QSPI interface to CLOCK the 68HC11/16/L11/PIC16C42. The 68L11 is for interfacing to the AD7853/AD7853L when the supply The SYNC SYNC SIGNAL TO GATE line is not used and is tied to DGND. The Controller is config- THE SCLK ured as the master, by setting the MSTR bit in the SPCR to 1, and thus provides the serial clock on the SCK pin ...
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... The BUSY signal only indicates when the conversion is finished and may not be required. The data access and hold times of the ADSP-21xx and the AD7853/ AD7853L allows for a CLKIN of 4 MHz/1.8 MHz at both 5 V and 3 V supplies. OPTIONAL 4MHz/1 ...
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... Digital and analog ground planes should only be joined in one place. If the AD7853/AD7853L is the only device requiring an AGND to DGND connection, then the ground planes should be connected at the AGND and DGND pins of the AD7853/AD7853L ...
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... Mode 1 (2-Wire 8051 Interface Mode 2 (3-Wire SPI/QSPI Interface Mode Mode 3 (QSPI Interface Mode Modes 4 and 5 (Self-Clocking Modes CONFIGURING THE AD7853/AD7853L . . . . . . . . . . . . 27 AD7853/AD7853L as a Read-Only ADC . . . . . . . . . . . . 27 Writing to the AD7853/AD7853L . . . . . . . . . . . . . . . . . . 28 Interface Modes 2 and 3 Configuration . . . . . . . . . . . . . . 28 Interface Mode 1 Configuration . . . . . . . . . . . . . . . . . . . . 29 Interface Modes 4 and 5 Configuration . . . . . . . . . . . . . . 29 MICROPROCESSOR INTERFACING . . . . . . . . . . . . . . . 30 AD7853/AD7853L to 8XC51/PIC17C42 Interface . . . . . 30 AD7853/AD7853L to 68HC11/16/L11/PIC16C42 Interface ...
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... AD7853/AD7853L PIN 1 0.016 (0.41) PIN 1 0.01 (0.254) 0.006 (0.15) PIN 1 0.008 (0.203) 0.002 (0.050) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24-Lead Plastic DIP (N-24 0.260 0.001 (6.61 0.03 1.228 (31.19) 1.226 (31.14) 0.130 (3.30) 0.128 (3.25) SEATING PLANE 0.02 (0.5) 0.11 (2.79) 0.07 (1.78) 0.09 (2.28) 0.05 (1.27) NOTES 1. LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH 2. PLASTIC LEADS WILL BE EITHER SOLDER DIPPED OR TIN PLATED IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS ...