AD7853 Analog Devices, AD7853 Datasheet - Page 21

• Manufacturer Part Number: AD7853
• Description: 3 V to 5 V Single Supply, 200 kSPS, 12-Bit, Serial Sampling ADC
• Manufacturer: Analog Devices

Specifications of AD7853

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 200kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (Vref) p-p,Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: DIP,SOIC

REV. B
capacitors, one of which is trimmed when an offset or gain cali-
bration is performed. Again it is the ratio of these capacitors to
the capacitors in the DAC that is critical and the calibration
algorithm ensures that this ratio is at a specified value for both
the offset and gain calibrations.
In Bipolar Mode the midscale error is adjusted for an offset
calibration and the positive full-scale error is adjusted for the
gain calibration; in Unipolar Mode the zero-scale error is ad-
justed for an offset calibration and the positive full-scale error is
adjusted for a gain calibration.
Self-Calibration Timing
The diagram of Figure 27 shows the timing for a full self-
calibration. Here the BUSY line stays high for the full length of
the self-calibration. A self-calibration is initiated by bringing the
CAL pin low (which initiates an internal reset) and then high
again or by writing to the control register and setting the STCAL
bit to 1 (note that if the part is in a power-down mode, the CAL
pulsewidth must take account of the power-up time). The BUSY line
is triggered high from the rising edge of CAL (or the end of the
write to the control register if calibration is initiated in soft-
ware), and BUSY will go low when the full self-calibration is
complete after a time t
For the self-(gain + offset), self-offset and self-gain calibrations,
the BUSY line will be triggered high by the rising edge of the
CAL signal (or the end of the write to the control register if
calibration is initiated in software) and will stay high for the full
duration of the self-calibration. The length of time that the
BUSY is high for will depend on the type of self-calibration that
is initiated. Typical figures are given in Table IX. The timing
diagrams for the other self-calibration options will be similar to
that outlined in Figure 27.
System Calibration Description
System calibration allows the user to take out system errors
external to the AD7853/AD7853L as well as calibrate the errors
of the AD7853/AD7853L itself. The maximum calibration
range for the system offset errors is 5% of V
system gain errors is 2.5% of V
mum allowable system offset voltage applied between the
AIN(+) and AIN(–) pins for the calibration to adjust out this
error is 0.05
AIN(–) or 0.05
the maximum allowable system full-scale voltage, in unipolar
mode, that can be applied between AIN(+) and AIN(–) for the
calibration to adjust out this error is V
the AIN(+) can be V
0.025
BUSY (O/P)
Figure 27. Timing Diagram for Full Self-Calibration
V
(I/P)
REF
above AIN(–)). If the system offset or system gain
V
V
REF
t
REF
1
REF
(i.e., the AIN(+) can be 0.05 V
CAL
below AIN(–)). For the system gain error
t
+ 0.025
15
as shown in Figure 27.
REF
t
t
15
CAL
V
t
= 2.5
1
. This means that the maxi-
REF
= 125013
= 100ns MIN,
REF
t
t
CLKIN
CAL
above AIN(–) or V
t
CLKIN
MAX,
0.025
REF
and for the
V
REF
REF
above
(i.e.,
REF
–
–21–
errors are outside the ranges mentioned, the system calibration
algorithm will reduce the errors as much as the trim range allows.
Figures 33 through 35 illustrate why a specific type of system
calibration might be used. Figure 33 shows a system offset cali-
bration (assuming a positive offset) where the analog input
range has been shifted upwards by the system offset after the
system offset calibration is completed. A negative offset may
also be accounted for by a system offset calibration.
Figure 29 shows a system gain calibration (assuming a system
full scale greater than the reference voltage) where the analog
input range has been increased after the system gain calibration
is completed. A system full-scale voltage less than the reference
voltage may also be accounted for a by a system gain calibration.
Finally in Figure 30 both the system offset and gain are ac-
counted for by the system offset followed by a system gain cali-
bration. First the analog input range is shifted upwards by the
positive system offset and then the analog input range is ad-
justed at the top end to account for the system full scale.
V
SYS OFFSET
SYS FULL S.
V
SYS OFFSET
V
REF
MAX SYSTEM FULL SCALE
REF
REF
MAX SYSTEM FULL SCALE
IS 2.5% FROM V
SYS F. S.
AGND
– 1LSB
MAX SYSTEM OFFSET
– 1LSB
IS 2.5% FROM V
MAX SYSTEM OFFSET
AGND
– 1LSB
AGND
IS 5% OF V
IS 5% OF V
Figure 30. System (Gain + Offset) Calibration
Figure 28. System Offset Calibration
Figure 29. System Gain Calibration
REF
REF
REF
REF
ANALOG
INPUT
RANGE
ANALOG
INPUT
RANGE
ANALOG
INPUT
RANGE
SYSTEM OFFSET
FOLLOWED BY
CALIBRATION
CALIBRATION
SYSTEM GAIN
CALIBRATION
SYSTEM GAIN
SYSTEM OFFSET
CALIBRATION
AD7853/AD7853L
V
REF
V
REF
+ SYS OFFSET
V
V
SYS OFFSET
+ SYS OFFSET
SYS FULL S.
V
MAX SYSTEM FULL SCALE
REF
MAX SYSTEM FULL SCALE
REF
SYS OFFSET
REF
MAX SYSTEM FULL SCALE
IS
SYS F.S.
IS
– 1LSB
– 1LSB
IS
MAX SYSTEM OFFSET
– 1LSB
AGND
AGND
AGND
MAX SYSTEM OFFSET
2.5% FROM V
2.5% FROM V
IS 5% OF V
2.5% FROM V
IS
5% OF V
REF
REF
REF
REF
REF
ANALOG
INPUT
RANGE
ANALOG
INPUT
RANGE
ANALOG
INPUT
RANGE