AD7853 Analog Devices, AD7853 Datasheet - Page 18

• Manufacturer Part Number: AD7853
• Description: 3 V to 5 V Single Supply, 200 kSPS, 12-Bit, Serial Sampling ADC
• Manufacturer: Analog Devices

Specifications of AD7853

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 200kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (Vref) p-p,Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: DIP,SOIC

AD7853/AD7853L
POWER-DOWN OPTIONS
The AD7853 provides flexible power management to allow the
user to achieve the best power performance for a given through-
put rate. The power management options are selected by
programming the power management bits, PMGT1 and PMGT0,
in the control register and by use of the SLEEP pin. Table VI
summarizes the power-down options that are available and how
they can be selected by using either software, hardware or a
combination of both. The AD7853 can be fully or partially
powered down. When fully powered down, all the on-chip cir-
cuitry is powered down and I
down is selected, then all the on-chip circuitry except the reference
–78
–80
–82
–84
–86
–88
–90
0
AV
100mV p-p SINE WAVE ON AV
DD
Figure 22. PSRR vs. Frequency
= DV
ANALOG SUPPLY
AUTO POWER-
20
DD
DOWN AFTER
CONVERSION
AUTO CAL ON
POWER-UP
= 3.3V/5.0V,
UNIPOLAR RANGE
INPUT FREQUENCY – kHz
0V TO 2.5V
+3V
40
DV
INPUT
DD
CURRENT, I = 1.5mA TYP
0.01 F
DD
is 1 A typ. If a partial power-
0.1 F
DD
10 F
0.01 F
60
0.1 F
REF-192
5.0V
AIN(+)
AIN(–)
AMODE
C
C
SLEEP
POLARITY
CAL
AGND
DGND
REF1
REF2
80
Figure 23. Typical Low Power Circuit
3.3V
AV
DD
OPTIONAL EXTERNAL
REFERENCE
REF
AD7853L
DV
IN
100
0.1 F
DD
/REF
OUT
0.1 F
MASTER CLOCK INPUT
INTERNAL
REFERENCE
–18–
CONVST
is powered down and I
tial power-down does not give any significant improvement in
throughput with a power-down between conversions. This is
discussed in the next section–Power-Up Times. However, a
partial power-down does allow the on-chip reference to be used
externally even though the rest of the AD7853 circuitry is pow-
ered down. It also allows the AD7853 to be powered up faster
after a long power-down period when using the on-chip refer-
ence (See Power-Up Times–Using On-Chip Reference).
When using the SLEEP pin, the power management bits PMGT1
and PMGT0 should be set to zero (default status on power-up).
Bringing the SLEEP pin logic high ensures normal operation,
and the part does not power down at any stage. This may be
necessary if the part is being used at high throughput rates when
it is not possible to power down between conversions. If the user
wishes to power down between conversions at lower throughput
rates (i.e. <100 kSPS for the AD7853) to achieve better power
performances, then the SLEEP pin should be tied logic low.
If the power-down options are to be selected in software only,
then the SLEEP pin should be tied logic high. By setting the
power management bits PMGT1 and PMGT0 as shown in
Table VI, a Full Power-Down, Full Power-Up, Full Power-
Down Between Conversions, and a Partial Power-Down Be-
tween Conversions can be selected.
A typical connection diagram for a low power application is
shown in Figure 23 (AD7853L is the low power version of the
AD7853).
CLKIN
SYNC
DOUT
1.8MHz OSCILLATOR
SCLK
SM1
SM2
DIN
SERIAL CLOCK INPUT
SERIAL DATA OUTPUT
CONVERSION
START INPUT
SELECTION BITS
SERIAL MODE
100kHz PULSE
GENERATOR
DD
DIN AT DGND
=> NO WRITING
THREE-WIRE
SELECTED
is 400 A typ. The choice of full or par-
TO DEVICE
MODE
LOW POWER
C/ P
REV. B