AD7853 Analog Devices, AD7853 Datasheet - Page 4

• Manufacturer Part Number: AD7853
• Description: 3 V to 5 V Single Supply, 200 kSPS, 12-Bit, Serial Sampling ADC
• Manufacturer: Analog Devices

Specifications of AD7853

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 200kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (Vref) p-p,Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: DIP,SOIC

AD7853/AD7853L
TIMING SPECIFICATIONS
Parameter
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
NOTES
Descriptions that refer to SCLK (rising) or SCLK (falling) edges here are with the POLARITY pin HIGH. For the POLARITY pin LOW then the opposite edge of
SCLK will apply.
1
2
3
4
5
6
7
8
9
Specifications subject to change without notice.
Sample tested at +25 C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
Mark/Space ratio for the master clock input is 40/60 to 60/40.
For Interface Modes 1, 2, 3 the SCLK max frequency will be 4 MHz. For Interface Modes 4 and 5 the SCLK will be an output and the frequency will be f
The CONVST pulsewidth will apply here only for normal operation. When the part is in power-down mode, a different CONVST pulsewidth will apply (see Power-
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
For self-clocking mode (Interface Modes 4, 5) the nominal SCLK high and low times will be 0.5 t
t
t
The typical time specified for the calibration times is for a master clock of 4 MHz. For the L version the calibration times will be longer than those quoted here due to
CLKIN
SCLK
1
2
CONVERT
3
4
5
5A
6
7
8
9
10
11
11A
12
13
14
15
16
CAL
CAL1
CAL2
Table X and timing diagrams for different interface modes and calibration.
Down section).
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t
quish time of the part and is independent of the bus loading.
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the timing characteristics is the true delay of the part
in turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed the user can drive the DIN line knowing that a bus conflict will
not occur.
the 1.8/1 MHz master clock.
12
14
4
5
5
6
6
7
8
5
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
9
9
9
3
2
5 V
500
4
1.8
1
4
f
100
50
4.6
10 (18)
–0.4 t
0.6 t
50
50
75
40
20
0.4 t
0.4 t
30
30/0.4 t
50
50
90
50
2.5 t
2.5 t
31.25
27.78
3.47
CLKIN
0.4 t
SCLK
SCLK
SCLK
CLKIN
CLKIN
Limit at T
SCLK
SCLK
(A, B Versions)
SCLK
MIN
, T
1
MAX
3 V
500
4
1.8
1
4
f
100
90
4.6
10 (18)
–0.4 t
0.6 t
90
90
115
60
30
0.4 t
0.4 t
50
50/0.4 t
50
50
130
90
2.5 t
2.5 t
31.25
27.78
3.47
CLKIN
T
(AV
0.4 t
MAX
SCLK
SCLK
SCLK
CLKIN
CLKIN
DD
, unless otherwise noted)
SCLK
SCLK
= DV
SCLK
DD
= +3.0 V to +5.5 V; f
Units
kHz min
MHz max
MHz max
MHz max
MHz max
MHz max
ns min
ns max
ns min
ns min/max
ns min
ns max
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min/max
ns max
ns max
ns max
ns max
ns max
ns max
ms typ
ms typ
ms typ
s max
s max
–4–
Description
Master Clock Frequency
L Version, 0 C to +70 C, B Grade Only
L Version, –40 C to +85 C
Interface Modes 1, 2, 3 (External Serial Clock)
Interface Modes 4, 5 (Internal Serial Clock)
CONVST Pulsewidth
CONVST to BUSY Propagation Delay
Conversion Time = 18 t
L Version 1.8 (1) MHz CLKIN. Conversion Time = 18 t
SYNC to SCLK Setup Time (Noncontinuous SCLK Input)
SYNC to SCLK Setup Time (Continuous SCLK Input)
SYNC to SCLK Setup Time. Interface Mode 4 Only
Delay from SYNC until DOUT 3-State Disabled
Delay from SYNC until DIN 3-State Disabled
Data Access Time After SCLK
Data Setup Time Prior to SCLK
Data Valid to SCLK Hold Time
SCLK High Pulsewidth (Interface Modes 4 and 5)
SCLK Low Pulsewidth (Interface Modes 4 and 5)
SCLK to SYNC Hold Time (Noncontinuous SCLK)
(Continuous SCLK) Does Not Apply to Interface Mode 3
SCLK to SYNC Hold Time
Delay from SYNC until DOUT 3-State Enabled
Delay from SCLK to DIN Being Configured as Output
Delay from SCLK to DIN Being Configured as Input
CAL to BUSY Delay
CONVST to BUSY Delay in Calibration Sequence
Full Self-Calibration Time, Master Clock Dependent
(125013 t
Internal DAC Plus System Full-Scale Cal Time, Master Clock
Dependent (111114 t
System Offset Calibration Time, Master Clock Dependent
(13899 t
CLKIN
= 4 MHz for AD7853 and 1.8/1 MHz for AD7853L; T
CLKIN
CLKIN
SCLK
)
)
12
= 0.5 t
, quoted in the timing characteristics is the true bus relin-
CLKIN
CLKIN
DD
CLKIN
.
) and timed from a voltage level of 1.6 V. See
)
A
= T
CLKIN
CLKIN
REV. B
MIN
.
to