EVAL-AD7687CB Analog Devices Inc, EVAL-AD7687CB Datasheet - Page 22

• Manufacturer Part Number: EVAL-AD7687CB
• Description: BOARD EVAL FOR AD7687
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7687CB

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 250k
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 4mW @ 5 V, 100kSPS
• Voltage Supply Source: Single
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7687
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: Q2106448

AD7687
CHAIN MODE, NO BUSY INDICATOR
This mode can be used to daisy chain multiple AD7687s on a 3-
wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7687s is shown in
Figure 43 and the corresponding timing is given in Figure 44.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the BUSY indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
readback. When the conversion is complete, the MSB is output
SDO
ACQUISITION
SDI
A
t
= SDI
HSCKCNV
CNV
SCK
SDO
A
= 0
B
B
CONVERSION
t
SSCKCNV
t
CONV
t
EN
SDI
AD7687
t
t
HSDO
DSDO
CNV
SCK
A
D
D
1
A
B
15
15
Figure 44. Chain Mode, No BUSY Indicator Serial Interface Timing
Figure 43. Chain Mode, No BUSY Indicator Connection Diagram
t
SDO
SSDISCK
D
D
2
A
B
14
14
D
D
3
A
B
13
13
t
Rev. A | Page 22 of 28
SCKL
SDI
t
HSDISC
14
AD7687
CNV
SCK
B
t
D
D
15
CYC
A
B
onto SDO and the AD7687 enters the acquisition phase and
powers down. The remaining data bits stored in the internal
shift register are then clocked by subsequent SCK falling edges.
For each ADC, SDI feeds the input of the internal shift register
and is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 16 × N clocks are required to
readback the N ADCs. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate and, consequently more AD7687s in the chain, provided
the digital host has an acceptable hold time. The maximum
conversion rate may be reduced due to the total readback time.
For instance, with a 3 ns digital host set-up time and 3 V
interface, up to eight AD7687s running at a conversion rate of
220 kSPS can be daisy-chained on a 3-wire port.
1
1
ACQUISITION
t
SCK
SDO
t
t
SCKH
D
D
16
ACQ
A
B
0
0
D
17
A
15
D
18
CONVERT
DATA IN
CLK
A
14
DIGITAL HOST
30
D
31
A
1
D
32
A
0