EVAL-AD7687CB Analog Devices Inc, EVAL-AD7687CB Datasheet - Page 21

• Manufacturer Part Number: EVAL-AD7687CB
• Description: BOARD EVAL FOR AD7687
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7687CB

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 250k
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 4mW @ 5 V, 100kSPS
• Voltage Supply Source: Single
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7687
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: Q2106448

CS MODE 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7687 is connected
to an SPI-compatible digital host, which has an interrupt input,
and it is desired to keep CNV, which is used to sample the
analog input, independent of the signal used to select the data
reading. This requirement is particularly important in
applications where low jitter on CNV is desired.
The connection diagram is shown in Figure 41 and the
corresponding timing is given in Figure 42.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI could
be used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time and held low until the maximum conversion time to
guarantee the generation of the BUSY signal indicator. When
the conversion is complete, SDO goes from high impedance to
low. With a pull-up on the SDO line, this transition can be used
ACQUISITION
SDO
CNV
SCK
SDI
t
SSDICNV
t
HSDICNV
CONVERSION
t
CONV
t
EN
Figure 42. CS Mode 4-Wire with BUSY Indicator Serial Interface Timing
1
t
t
HSDO
DSDO
Rev. A | Page 21 of 28
D15
2
t
CYC
as an interrupt signal to initiate the data readback controlled by
the digital host. The AD7687 then enters the acquisition phase
and powers down. The data bits are then clocked out, MSB first,
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate provided it has an acceptable hold time. After the optional
17th SCK falling edge, or SDI going high, whichever is earlier,
the SDO returns to high impedance.
D14
3
ACQUISITION
Figure 41. CS Mode 4-Wire with BUSY Indicator Connection Diagram
t
ACQ
t
SDI
SCKL
t
AD7687
SCKH
15
CNV
SCK
t
SCK
SDO
16
D1
VIO
17
D0
47kΩ
CS1
CONVERT
DATA IN
IRQ
CLK
t
DIGITAL HOST
DIS
AD7687