EVAL-ADF4156EBZ1 Analog Devices Inc, EVAL-ADF4156EBZ1 Datasheet - Page 8

• Manufacturer Part Number: EVAL-ADF4156EBZ1
• Description: BOARD EVALUATION FOR ADF4156
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADF4156EBZ1

• Module/board Type: Evaluation Board
• For Use With/related Products: ADF4156
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q5595826; Q5830082A

ADF4156
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 11. While the
device is operating, SW1 and SW2 are usually closed switches
and SW3 is open. When a power-down is initiated, SW3 is
closed and SW1 and SW2 are opened. This ensures that the
REF
RF INPUT STAGE
The RF input stage is shown in Figure 12. It is followed by a
two-stage limiting amplifier to generate the current-mode logic
(CML) clock levels needed for the prescaler.
RF
RF
IN
IN
IN
pin is not loaded while the device is powered down.
A
B
REF
IN
NC
GENERATOR
POWER-DOWN
SW1
Figure 11. Reference Input Stage
CONTROL
BIAS
NO
Figure 12. RF Input Stage
NC
SW3
SW2
2kΩ
100kΩ
1.6V
BUFFER
2kΩ
TO R-COUNTER
AGND
AV
DD
Rev. A | Page 8 of 24
RF INT DIVIDER
The RF INT counter allows a division ratio in the PLL feedback
counter. Division ratios from 23 to 4095 are allowed.
INT, FRAC, MOD, AND R RELATIONSHIP
The INT, FRAC, and MOD values, in conjunction with the
R-counter, enable generating output frequencies that are spaced
by fractions of the phase frequency detector (PFD). See the RF
Synthesizer: A Worked Example section for more information.
The RF VCO frequency (RF
where RF
controlled oscillator (VCO).
where:
REF
D is the REF
T is the REF
R is the preset divide ratio of the binary 5-bit programmable
reference counter (1 to 32).
INT is the preset divide ratio of the binary 12-bit counter
(23 to 4095).
MOD is the preset fractional modulus (2 to 4095).
FRAC is the numerator of the fractional division (0 to MOD − 1).
RF R-COUNTER
The 5-bit RF R-counter allows the input reference frequency
(REF
the PFD. Division ratios from 1 to 32 are allowed.
INPUT STAGE
IN
FROM RF
RF
F
IN
PFD
is the reference input frequency.
) to be divided down to produce the reference clock to
OUT
= REF
OUT
= F
IN
IN
is the output frequency of an external voltage-
PFD
divide-by-2 bit (0 or 1).
doubler bit.
RF N-DIVIDER
IN
N-COUNTER
× (INT + (FRAC/MOD))
× [(1 + D)/(R × (1 + T))]
REG
INT
Figure 13. RF INT Divider
OUT
) equation is
MOD
REG
N = INT + FRAC/MOD
INTERPOLATOR
THIRD-ORDER
FRACTIONAL
VALUE
FRAC
TO PFD
(1)
(2)