EVAL-ADF4156EBZ1 Analog Devices Inc, EVAL-ADF4156EBZ1 Datasheet - Page 18

• Manufacturer Part Number: EVAL-ADF4156EBZ1
• Description: BOARD EVALUATION FOR ADF4156
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADF4156EBZ1

• Module/board Type: Evaluation Board
• For Use With/related Products: ADF4156
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q5595826; Q5830082A

ADF4156
In most cases, this method also provides faster lock times than
the bandwidth switching mode method. In extreme cases, where
cycle slips do not exist in the settling transient, the bandwidth
switching mode can be used.
Cycle Slip Reduction Mode
Cycle slips occur in integer-N/fractional-N synthesizers when
the loop bandwidth is narrow compared with the PFD frequency.
The phase error at the PFD inputs accumulates too fast for the
PLL to correct, and the charge pump temporarily pumps in the
wrong direction. This slows down the lock time dramatically.
The ADF4156 contains a cycle slip reduction circuit to extend
the linear range of the PFD, allowing faster lock times without
requiring loop filter changes.
When the ADF4156 detects that a cycle slip is about to occur, it
turns on an extra charge-pump current cell. This either outputs
a constant current to the loop filter or removes a constant current
from the loop filter, depending on whether the VCO tuning
voltage needs to increase or decrease to acquire the new frequency.
As a result, the linear range of the PFD is increased. Stability is
maintained because the current is constant, not pulsed.
If the phase error increases to a point where another cycle slip
is likely, the ADF4156 turns on another charge-pump cell. This
process continues until the ADF4156 detects that the VCO
frequency is beyond the desired frequency. The extra charge-pump
cells then begin to turn off one by one until they are all turned
off and the frequency is settled.
Up to seven extra charge-pump cells can be turned on. In most
applications, this is sufficient to eliminate cycle slips altogether,
resulting in much faster lock times.
Setting Bit DB28 in the MOD/R register (R2) to 1 enables cycle
slip reduction. A 45% to 55% duty cycle is needed on the signal
at the PFD for CSR to operate correctly. Note that CSR cannot
be used if the phase detector polarity is set to negative; therefore,
a noninverting loop filter topology should be used with CSR.
Dynamic Bandwidth Switching Mode
The dynamic bandwidth switching mode involves increasing
the loop filter bandwidth for a set time at the beginning of the
locking transient. This is achieved by boosting the charge-pump
current from the set value in Register R2 to the maximum setting.
To maintain loop stability during this period, it is necessary to
modify the loop filter by adding a switch and resistor. When the
new frequency is programmed to the ADF4156 in this mode, three
events occur simultaneously to put the device in wideband mode:
•
•
•
A timeout counter is started.
The charge-pump current is boosted from its set current to
the maximum setting.
The fast-lock switch (available via MUXOUT) is activated.
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The timeout counter in Register R4 defines the period that the
device is kept in wideband mode. During wideband mode, the
PLL acquires lock faster due to the wider loop filter bandwidth.
Stability is maintained at the optimal 45° setting due to the use
of the extra resistor in the loop filter.
When the timeout counter times out, the charge-pump current
is reduced from the maximum setting to its set current, and the
fast-lock switch is deactivated. The device is then in narrow-
band mode, and spurs are attenuated.
To ensure optimum lock time, the timeout counter should be
set to time out when the PLL is close to the final frequency. If
the switch is deactivated, a spike in the settling transient will be
observed due to charge insertion from the switch. Because the
PLL is in narrow-band mode, this spike can take some time to
settle out. This is one of the disadvantages of the bandwidth
switching mode compared with the cycle slip reduction mode.
Fast Lock: An Example
If a PLL has a reference frequency of 13 MHz, a f
and a required lock time of 50 μs, the PLL is set to wide bandwidth
for 40 μs.
If the time set for the wide bandwidth is 40 μs, then
Therefore, 520 must be loaded into Bits DB[18:7] of Register R4.
The clock divider mode bits (DB[20:19]) in Register R4 must also
be set to 01 to activate this mode. To activate the fast-lock switch
on the MUXOUT pin, the MUXOUT control bits (DB[30:27])
in Register R0 must be set to 1100.
Fast Lock: Loop Filter Topology
To use fast-lock mode, an extra connection from the PLL to the
loop filter is needed. The damping resistor in the loop filter
must be reduced to ¼ of its value while in wide bandwidth
mode. This is required because the charge-pump current is
increased by 16 while in wide bandwidth mode and stability
must be ensured. When the ADF4156 is in fast-lock mode (that
is, when the fast-lock switch is programmed to appear at the
MUXOUT pin), the MUXOUT pin is automatically shorted to
ground. The following two topologies can be used:
•
•
Fast-Lock Timer Value = Time in Wide Bandwidth × f
Fast-Lock Timer Value = 40 μs × 13 MHz = 520
Topology 1: Divide the damping resistor (R1) into two
values (R1 and R1A) that have a ratio of 1:3 (see Figure 22).
Topology 2: Connect an extra resistor (R1A) directly from
MUXOUT, as shown in Figure 23. The extra resistor must
be chosen such that the parallel combination of an extra
resistor and the damping resistor (R1) is reduced to ¼ of
the original value of R1 (see Figure 23).
PFD
of 13 MHz,
PFD