EVAL-ADF4156EBZ1 Analog Devices Inc, EVAL-ADF4156EBZ1 Datasheet

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EVAL-ADF4156EBZ1

Manufacturer Part Number
EVAL-ADF4156EBZ1
Description
BOARD EVALUATION FOR ADF4156
Manufacturer
Analog Devices Inc
Datasheet

Specifications of EVAL-ADF4156EBZ1

Module/board Type
Evaluation Board
For Use With/related Products
ADF4156
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q5595826
Q5830082A
FEATURES
RF bandwidth to 6 GHz
2.7 V to 3.3 V power supply
Separate V
Programmable fractional modulus
Programmable charge-pump currents
3-wire serial interface
Digital lock detect
Power-down mode
Pin compatible with ADF4110/ADF4111/ADF4112/ADF4113,
Programmable RF output phase
Loop filter design possible with ADIsimPLL
Cycle slip reduction for faster lock times
APPLICATIONS
CATV equipment
Base stations for mobile radio (WiMAX, GSM, PCS, DCS,
Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANs, PMR
Communications test equipment
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
ADF4106, ADF4153, and ADF4154 frequency synthesizers
SuperCell 3G, CDMA, WCDMA)
P
pin allows extended tuning voltage
MUXOUT
CLOCK
REF
DATA
CE
LE
IN
ADF4156
HIGH Z
REGISTER
OUTPUT
32-BIT
DATA
DOUBLER
MUX
×2
AGND
V
DGND
SD
V
R
N
DD
DD
DIV
DIV
6 GHz Fractional-N Frequency Synthesizer
OUT
FUNCTIONAL BLOCK DIAGRAM
DGND
R-COUNTER
5-BIT
DETECT
LOCK
FRACTION
INTERPOLATOR
REG
THIRD-ORDER
FRACTIONAL
AV
DD
Figure 1.
DV
MODULUS
DIVIDER
DD
REG
/2
V
P
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
GENERAL DESCRIPTION
The ADF4156 is a 6 GHz fractional-N frequency synthesizer
that implements local oscillators in the upconversion and
downconversion sections of wireless receivers and transmitters.
It consists of a low noise digital phase frequency detector
(PFD), a precision charge pump, and a programmable reference
divider. There is a Σ-Δ based fractional interpolator to allow
programmable fractional-N division. The INT, FRAC, and
MOD registers define an overall N divider (N = (INT +
(FRAC/MOD))). The RF output phase is programmable for
applications that require a particular phase relationship between
the output and the reference. The ADF4156 also features cycle
slip reduction circuitry, leading to faster lock times without the
need for modifications to the loop filter.
Control of all on-chip registers is via a simple 3-wire interface.
The device operates with a power supply ranging from 2.7 V to
3.3 V and can be powered down when not in use.
CPGND
+
FREQUENCY
N-COUNTER
DETECTOR
INTEGER
PHASE
REG
RFCP4
©2006–2009 Analog Devices, Inc. All rights reserved.
RFCP3 RFCP2
CURRENT
SETTING
REFERENCE
CHARGE
PUMP
R
SET
RFCP1
CSR
CP
RF
RF
ADF4156
IN
IN
A
B
www.analog.com

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EVAL-ADF4156EBZ1 Summary of contents

Page 1

FEATURES RF bandwidth to 6 GHz 2 3.3 V power supply Separate V pin allows extended tuning voltage P Programmable fractional modulus Programmable charge-pump currents 3-wire serial interface Digital lock detect Power-down mode Pin compatible with ADF4110/ADF4111/ADF4112/ADF4113, ADF4106, ...

Page 2

ADF4156 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Timing Specifications .................................................................. 4 Absolute Maximum Ratings ............................................................ 5 Thermal Impedance ..................................................................... 5 ESD ...

Page 3

... This value can be used to calculate the phase noise for any application. Use the formula −211 + 10 log(f seen at the VCO output. The value given is the lowest noise mode. 5 The phase noise is measured with the EVAL-ADF4156EBZ1 evaluation board and the Agilent E5500 phase noise system ...

Page 4

ADF4156 TIMING SPECIFICATIONS 2 3 Table 2. Parameter Limit MIN MAX ...

Page 5

ABSOLUTE MAXIMUM RATINGS T = 25°C, GND = AGND = DGND = unless otherwise noted. Table 3. Parameter V to GND GND ...

Page 6

ADF4156 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS SET CPGND 3 14 ADF4156 TOP VIEW AGND 4 13 (Not to Scale ...

Page 7

TYPICAL PERFORMANCE CHARACTERISTICS PFD = 25 MHz, loop bandwidth = 20 kHz, reference = 100 MHz, I phase noise system –5 – 4/5 –15 –20 –25 –30 –35 – ...

Page 8

ADF4156 CIRCUIT DESCRIPTION REFERENCE INPUT SECTION The reference input stage is shown in Figure 11. While the device is operating, SW1 and SW2 are usually closed switches and SW3 is open. When a power-down is initiated, SW3 is closed and ...

Page 9

PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP The PFD takes inputs from the R-counter and N-counter and produces an output proportional to the phase and frequency difference between them. Figure simplified schematic of the phase frequency detector. ...

Page 10

ADF4156 REGISTER MAPS RE- MUXOUT CONTROL SERVED DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 ...

Page 11

FRAC/INT REGISTER, R0 With the control bits (Bits[2:0]) of Register R0 set to 000, the on-chip FRAC/INT register is programmed. Figure 17 shows the input data format for programming this register. 12-Bit Integer Value (INT) These 12 bits control what ...

Page 12

ADF4156 PHASE REGISTER, R1 With the control bits (Bits[2:0]) of Register R1 set to 001, the on-chip phase register is programmed. Figure 18 shows the input data format for programming this register. 12-Bit Phase Value These 12 bits control what ...

Page 13

MOD/R REGISTER, R2 With the control bits (Bits[2:0]) of Register R1 set to 010, the on-chip MOD/R register is programmed. Figure 19 shows the input data format for programming this register. Noise and Spur Mode The noise modes on the ...

Page 14

ADF4156 NOISE CURRENT MODE SETTING DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 ...

Page 15

FUNCTION REGISTER, R3 With the control bits (Bits[2:0]) of Register R2 set to 011, the on-chip function register is programmed. Figure 20 shows the input data format for programming this register. Counter Reset DB3 is the counter reset bit for ...

Page 16

ADF4156 CLK DIV REGISTER, R4 With the control bits (Bits[2:0]) of Register R3 set to 100, the on-chip clock divider register (R4) is programmed. Figure 21 shows the input data format for programming this register. 12-Bit Clock Divider Value The ...

Page 17

RF SYNTHESIZER: A WORKED EXAMPLE The following equation governs how the synthesizer should be programmed [INT + (FRAC/MOD)] × [F OUT where the RF frequency output. OUT INT is the integer division factor. FRAC is the ...

Page 18

ADF4156 In most cases, this method also provides faster lock times than the bandwidth switching mode method. In extreme cases, where cycle slips do not exist in the settling transient, the bandwidth switching mode can be used. Cycle Slip Reduction ...

Page 19

... Therefore, a look-up table of phase values corresponding to each frequency can be constructed for use when programming the ADF4156. Spur Interval The evaluation software has a sweep function to sweep the Channel step/2 phase word so that the user can observe the spur levels on a Channel step/3 spectrum analyzer ...

Page 20

ADF4156 PHASE RESYNC The output of a fractional-N PLL can settle to any MOD phase offset with respect to the input reference, where MOD is the fractional modulus. The phase resync feature in the ADF4156 is used to produce a ...

Page 21

INTERFACING The ADF4156 has a simple SPI-compatible serial interface for writing to the device. CLOCK, DATA, and LE control the data transfer. When latch enable (LE) is high, the 29 bits that have been clocked into the input register on ...

Page 22

ADF4156 OUTLINE DIMENSIONS 0.15 0.05 PIN 1 INDICATOR 12° MAX 1.00 0.85 0.80 SEATING PLANE 5.10 5.00 4. 4.50 6.40 4.40 BSC 4. PIN 1 1.20 MAX 0.20 0.09 8° 0.30 0° 0.65 0.19 SEATING BSC ...

Page 23

... ADF4156BCPZ-RL −40°C to +85°C 1 ADF4156BCPZ-RL7 −40°C to +85°C 1 EVAL-ADF4156EBZ1 RoHS Compliant Part. Package Description 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] ...

Page 24

ADF4156 NOTES 2 Purchase of licensed I C components of Analog Devices, Inc., or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I Patent Rights to use these components ...

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