DK-CYCII-2C20N Altera, DK-CYCII-2C20N Datasheet - Page 48

• Manufacturer Part Number: DK-CYCII-2C20N
• Description: CYCLONE II STARTER KIT EP2C20N
• Manufacturer: Altera
• Series: Cyclone® IIr
• Type: FPGAr

Specifications of DK-CYCII-2C20N

• Contents: Dev Board, Quartus®II Web Edition, Nios®II Web Edition, Cables, Accessories, Reference Designs and Demos
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone
• Silicon Core Number: EP2C
• Silicon Family Name: Cyclone II
• Rohs Compliant: Yes
• For Use With/related Products: Cyclone®II FPGAs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1736

SD Card Music Player
Figure 6–3. SD Music Player Block Diagram
6–6
Cyclone II FPGA Starter Development Kit User Guide
Because the audio CODEC is configured in the slave mode, external
circuitry must provide the ADC/DAC serial bit clock (BCK) and left/right
channel clock (LRCK) to the audio CODEC. The block diagram
(Figure
controller for clock generation and data flow control. The audio DAC
controller is integrated into the Avalon bus architecture, so that the
Nios II processor can control the application.
During operation, the Nios II processor checks if the FIFO memory of the
audio DAC controller becomes full. If the FIFO is not full, the processor
reads a 512-byte sector and sends the data to the FIFO of the audio DAC
controller via the Avalon bus. The audio DAC controller uses a 48 kHz
sample rate to send the data and clock signals to the audio CODEC. The
design also mixes the data from the Mic In port with data from the Line
In port for the Karaoke-style effects.
File Locations
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Demonstration Setup
To set up the demonstration, perform the following steps:
Project directory: CII_Starter_SD_Card_Audio
Bit stream used: CII_Starter_SD_Card_Audio.sof (or .pof)
Nios II Workspace: CII_Starter_SD_Card_Audio
6–3) shows that the sample design provides an audio DAC
Altera Corporation
October 2006