STEVAL-ISQ002V1 STMicroelectronics, STEVAL-ISQ002V1 Datasheet - Page 108

• Manufacturer Part Number: STEVAL-ISQ002V1
• Description: BOARD EVAL BASED ON ST72264G1
• Manufacturer: STMicroelectronics

Specifications of STEVAL-ISQ002V1

• Main Purpose: Interface, PMBus
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ST72F264
• Primary Attributes: The PMBus™ Interface Using the ST7 I2C Peripheral
• Secondary Attributes: Firmware in C Language
• Product: Power Management Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-6423

ST72260Gx, ST72262Gx, ST72264Gx
I
Figure 59. Transfer Sequencing
Legend: S=Start, S
EVx=Event (with interrupt if ITE=1)
108/172
10-bit Master transmitter
2
7-bit Slave receiver:
S Address
7-bit Slave transmitter:
S Address
7-bit Master receiver:
7-bit Master transmitter:
10-bit Slave receiver:
S Header
10-bit Slave transmitter:
10-bit Master receiver:
S
S
S
C BUS INTERFACE (Cont’d)
EV5
EV5
EV5
EV1: EVF=1, ADSL=1, cleared by reading SR1 register.
EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading SR1 register. BTF is cleared by releasing the
lines (STOP=1, STOP=0) or by writing DR register (DR=FFh). Note: If lines are released by
STOP=1, STOP=0, the subsequent EV4 is not seen.
EV4: EVF=1, STOPF=1, cleared by reading SR2 register.
EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register.
EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1).
EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register.
Address
Address
Header
A
A
A
EV1
EV1 EV3
Address
r
= Repeated Start, P=Stop, A=Acknowledge, NA=Non-acknowledge,
A
A
A
Data1
EV6
EV6 EV8
EV9
A
Data1
S
Address
S
r
Data1
r
EV1
Header A
EV5
A
Data1
EV2
Data1
A
Header
A
A
Data2
EV3
EV7
EV6 EV8
A
EV1 EV3
A
Data2
EV8
A
Data2
EV2
EV6
A
Data2
Data1
Data1
EV2
A
.....
A
Data1
EV3
EV7
DataN
.....
A
A
A
EV8
EV8
A
EV3
DataN
.....
.....
EV7
A
....
DataN
.....
.....
.
DataN
EV2
DataN
.....
A
DataN
DataN
EV2
P
NA
NA
DataN
A
EV4
P
EV3-1
EV7
EV3-1
A
A
EV4
A
EV8
EV8
P
P
P
EV7
EV4
P
P
EV4
P