KSZ8851SNL-BBE-EVAL Micrel Inc, KSZ8851SNL-BBE-EVAL Datasheet - Page 50

BOARD EVAL MAC/PHY FOR KSZ8851

KSZ8851SNL-BBE-EVAL

Manufacturer Part Number
KSZ8851SNL-BBE-EVAL
Description
BOARD EVAL MAC/PHY FOR KSZ8851
Manufacturer
Micrel Inc
Series
LinkMD®r

Specifications of KSZ8851SNL-BBE-EVAL

Design Resources
BeagleBoard Zippy2
Main Purpose
Interface, Ethernet Controller (PHY and MAC)
Embedded
No
Utilized Ic / Part
KSZ8851SNL
Primary Attributes
1 Port, 100BASE-TX/10BASE-T
Secondary Attributes
SPI Interface, LinkMD Cable Diagnostics
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
576-3602
KSZ8851SNL-BBE-EVL
ZIPPY2

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Part Number
Manufacturer
Quantity
Price
Part Number:
KSZ8851SNL-BBE-EVAL
Manufacturer:
Micrel Inc
Quantity:
135
Receive Control Register 2 (0x76 – 0x77): RXCR2
This register holds control information programmed by the CPU to control the receive function.
August 2009
Micrel, Inc.
Bit
6
5
4
3
2
1
0
Bit
15-8
7-5
4
3
2
0x0
0x0
0x0
0x0
0x0
0x0
0x0
-
0x0
0x0
0x1
Default Value
Default Value
0x0
R/W
RW
RW
RW
RW
RW
RW
RW
R/W
RO
WO
RW
RW
RW
Description
RXME Receive Multicast Enable
When this bit is set, the RX module receives all the multicast frames (including broadcast
frames).
RXUE Receive Unicast Enable
When this bit is set, the RX module receives unicast frames that match the 48-bit Station
MAC address of the module.
RXAE Receive All Enable
When this bit is set, the KSZ8851SNL receives all incoming frames, regardless of the
frame’s destination address (see Address Filtering Scheme in Table 3 for detail).
Reserved
Reserved
RXINVF Receive Inverse Filtering
When this bit is set, the KSZ8851SNL receives function with address check operation in
inverse filtering mode (see Address Filtering Scheme in Table 3 for detail).
RXE Receive Enable
When this bit is set, the RX block is enabled and placed in a running state.
When this bit is cleared, the receive process is placed in the stopped state upon
completing reception of the current frame.
Description
Reserved
SRDBL SPI Receive Data Burst Length
These three bits are used to define for SPI receive data burst length during DMA
operation from the host CPU to access RXQ frame buffer.
000: 4 Bytes data burst
010: 16 Bytes data burst
100: Single frame data burst
Note: It needs RXQ FIFO Read command byte before each data burst.
IUFFP IPV4/IPV6/UDP Fragment Frame Pass
When this bit is set, the KSZ8851SNL will pass the checksum check at receive side for
IPv4/IPv6 UDP frame with fragment extension header.
When this bit is cleared, the KSZ8851SNL will perform checksum operation based on
configuration and doesn’t care whether it’s a fragment frame or not.
RXIUFCEZ Receive IPV4/IPV6/UDP Frame Checksum Equal Zero
When this bit is set, the KSZ8851SNL will pass the filtering for Ipv4/IPV6 UDP frame with
UDP checksum equal to zero.
When this bit is cleared, the KSZ8851SNL will drop IPV4/IPV6 UDP packet with UDP
checksum equal to zero.
UDPLFE UDP Lite Frame Enable
When this bit is set, the KSZ8851SNL will check the checksum at receive side and
generate the checksum at transmit side for UDP Lite frame.
When this bit is cleared, the KSZ8851SNL will pass the checksum check at receive side
and skip the checksum generation at transmit side for UDP Lite frame.
50
001: 8 Bytes data burst
011: 32 Bytes data burst
101-111: NA (reserved)
KSZ8851SNL/SNLI
M9999-083109-2.0

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