KSZ8851SNL-BBE-EVAL Micrel Inc, KSZ8851SNL-BBE-EVAL Datasheet - Page 23

• Manufacturer Part Number: KSZ8851SNL-BBE-EVAL
• Description: BOARD EVAL MAC/PHY FOR KSZ8851
• Manufacturer: Micrel Inc
• Series: LinkMD®r

Specifications of KSZ8851SNL-BBE-EVAL

• Design Resources: BeagleBoard Zippy2
• Main Purpose: Interface, Ethernet Controller (PHY and MAC)
• Embedded: No
• Utilized Ic / Part: KSZ8851SNL
• Primary Attributes: 1 Port, 100BASE-TX/10BASE-T
• Secondary Attributes: SPI Interface, LinkMD Cable Diagnostics
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-3602; KSZ8851SNL-BBE-EVL; ZIPPY2

SPI Internal I/O Registers Access Operation Timing
As shown in Figures 7 and 8 illustrate the SPI internal I/O registers read and write operation timing, the first two command
byte 0/1 contain opcode (00: read command, 01: write command), B[3:0] Byte enable bits to indicate which data byte is
available in data phase (1: byte enable, 0: byte disable) and A[7:2] address bits to access register location. The following
is data phase either 1, 2, 3, or 4 bytes depending on B[3:0] setting.
SPI TXQ/RXQ FIFOs Access Operation Timing
As shown in Figures 9 and 10 illustrate the SPI TXQ/RXQ FIFOs write and read operation timing, the first command byte
August 2009
Micrel, Inc.
Note: The Start DMA Access bit 3 in RXQCR register must set to “1” before FIFO
read/write commands. This bit must be clear to “0” when DMA operation is finished.
RXQ FIFO Read
TXQ FIFO Write
SPI Operation
(12 KByte)
(6 KByte)
Table 5. SPI Operation for TXQ/RXQ FIFO Access
Figure 7. Internal I/O Register Read Timing
Figure 8. Internal I/O Register Write Timing
Opcode
Command Phase (SI pin)
1 0
1 1
Byte 0 [7:0]
X X X X X X
X X X X X X
Don’t care bits
23
(DMA read data on SO pin)
(DMA write data on SI pin)
(SO or SI pins)
1 to 12 KBytes
1 to 6 KBytes
Data Phase
KSZ8851SNL/SNLI
M9999-083109-2.0