MT4LSDT864HG-133G2 Micron Technology Inc, MT4LSDT864HG-133G2 Datasheet - Page 4

• Manufacturer Part Number: MT4LSDT864HG-133G2
• Description: MODULE SDRAM 64MB 144SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT4LSDT864HG-133G2

• Memory Type: SDRAM
• Memory Size: 64MB
• Speed: 133MHz
• Package / Case: 144-SODIMM
• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 144SODIMM
• Device Core Size: 64b
• Organization: 8Mx64
• Total Density: 64MByte
• Chip Density: 128Mb
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 600mA
• Number Of Elements: 4
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 65C
• Operating Temperature Classification: Commercial
• Pin Count: 144
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 5:
Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 more information
09005aef80748a77
SD4C4_8_16X64HG.fm - Rev. C 6/04 EN
23, 24, 25, 26, 115, 116, 117,
70 (128MB), 103, 104, 105,
29, 30, 31,32, 33, 34,
PIN NUMBERS
109, 111, 112
65, 66, 67
106, 110
118
142
141
61
62
69
Pin Descriptions
RAS#, CAS#, WE#
DQMB0–DQMB7
(32MB, 64MB)
SYMBOL
BA0, BA1
(128MB)
A0–A11
A0–A12
CKE0
CK0
SDA
S0#
SCL
Output
Input/
TYPE
Input
Input
Input
Input
Input
Input
Input
Input
Command Inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
Clock: CK is driven by the system clock. All SDRAM input
signals are sampled on the positive edge of CK. CK also
increments the internal burst counter and controls the output
registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the
CK signal. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all device banks
idle), ACTIVE POWER-DOWN (row ACTIVE in any device bank)
or CLOCK SUSPEND operation (burst access in progress). CKE is
synchronous except after the device enters power-down and
self refresh modes, where CKE becomes asynchronous until
after exiting the same mode. The input buffers, including CK,
are disabled during power-down and self refresh modes,
providing low standby power.
Chip Select: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.
Input/Output Mask: DQMB is an input mask signal for write
accesses and an output enable signal for read accesses. Input
data is masked when DQMB is sampled HIGH during a WRITE
cycle. The output buffers are placed in a High-Z state (two-
clock latency) when DQMB is sampled HIGH during a READ
cycle.
Bank Address: BA0 and BA1 define to which device bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Address Inputs: Provide the row address for ACTIVE
commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out
of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines whether
the PRECHARGE applies to one device bank (A10 LOW, device
bank selected by BA0, BA1) or all device banks (A10 HIGH).
The address inputs also provide the op-code during a MODE
REGISTER SET command.
Serial Clock for Presence-Detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
Serial Presence-Detect Data: SDA is a bidirectional pin used to
transfer addresses and data into and out of the presence-
detect portion of the module.
4
32MB, 64MB, 128MB (x64, SR)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
144-PIN SDRAM SODIMM
DESCRIPTION
©2004 Micron Technology, Inc. All rights reserved.