MT9VDDT6472AY-40BF1 Micron Technology Inc, MT9VDDT6472AY-40BF1 Datasheet - Page 16

• Manufacturer Part Number: MT9VDDT6472AY-40BF1
• Description: MODULE DDR SDRAM 512MB 184-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT9VDDT6472AY-40BF1

• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 400MT/s
• Package / Case: 184-DIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1178; MT9VDDT6472AY-40BF1

Table 15: Capacitance
Note: 11; notes appear on pages 18–20
Table 16: DDR SDRAM Component Electrical Characteristics and
Notes: 1–5, 8, 12–15, 29, 31; notes appear on page 18–20; 0°C
pdf: 09005aef80a43e7d, source: 09005aef80a43d77
DDA9C16_32_64x72AG.fm - Rev. B 9/04 EN
AC CHARACTERISTICS
PARAMETER
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (1 V/ns)
Address and control input setup time (1 V/ns)
Address and control input hold time (0.5 V/ns)
Address and control input setup time (0.5 V/ns)
Address and Control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access
Data hold skew factor
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
PARAMETER
Input/Output Capacitance: DQs, DQSs
Input Capacitance: Command and Address, S0#
Input Capacitance: CK, CK#
Input Capacitance: CKE
Recommended AC Operating Conditions
128MB, 256MB, 512MB (x72, ECC, SR), PC3200
CL = 3
CL = 2.5
CL = 2
16
SYMBOL
t
t
CK (2.5)
t
t
t
t
t
DQSCK
t
t
t
CK (3)
CK (2)
DQSH
DQSQ
DIPW
t
t
DQSL
DQSS
t
t
t
t
MRD
t
T
t
t
t
t
DSH
t
t
t
t
QHS
RAP
t
IPW
RAS
t
t
DSS
t
t
t
RFC
QH
DH
AC
CH
HP
HZ
IH
IH
A
CL
DS
RC
LZ
IS
IS
F
S
F
S
+70°C; V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-Pin DDR SDRAM UDIMM
t
HP -
-0.70
MIN
0.45
0.45
1.75
0.35
0.35
0.72
2.20
-0.7
-0.6
DD
7.5
0.4
0.4
0.2
0.2
0.6
0.6
0.6
0.6
40
15
55
70
5
6
2
t
QHS
SYMBOL
= V
t
CH,
-40B
C
C
C
C
DD
IO
I 1
I 2
I 3
t
Q = +2.6V ±0.1V
CL
70,000
MAX
+0.70
+0.7
0.55
0.55
+0.6
0.40
1.28
0.50
7.5
13
13
MIN
18.0
10.5
18.0
4.0
UNITS
t
t
t
t
t
t
t
ns
CK
CK
ns
ns
ns
ns
ns
ns
ns
CK
CK
ns
CK
CK
CK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MAX
27.0
13.5
27.0
5.0
©2004 Micron Technology, Inc.
NOTES
UNITS
40, 46
40, 46
40, 46
23, 27
23, 27
22, 23
16, 38
16, 39
22, 23
26
26
27
30
12
12
12
12
31
46
pF
pF
pF
pF