ADP3208DJCPZ-RL ON Semiconductor, ADP3208DJCPZ-RL Datasheet - Page 31

• Manufacturer Part Number: ADP3208DJCPZ-RL
• Description: IC CTLR BUCK 7BIT 2PHASE 48LFCSP
• Manufacturer: ON Semiconductor

Specifications of ADP3208DJCPZ-RL

• Applications: Controller, Power Supplies for Next-Generation Intel Processors
• Voltage - Input: 3.3 ~ 22 V
• Number Of Outputs: 1
• Voltage - Output: 0.01 ~ 1.5 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Output Voltage: 10 mV
• Output Current: 40 A
• Input Voltage: 19 V
• Supply Current: 6 mA
• Switching Frequency: 300 KHz
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 10 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(I
Ramp Resistor Selection
PWM ramp. The value of this resistor is chosen to provide
the best combination of thermal balance, stability, and
transient response. Use the following expression to
determine a starting value:
A
A
R
C
the internal ramp voltage (see Equation 25). For stability and
noise immunity, keep the ramp size larger than 0.5 V. Taking
this into consideration, the value of R
selected as 280 kW.
follows:
decreased. If it is increased, stability and transient response
improves but thermal balance degrades. Conversely, if the
ramp size is decreased, thermal balance improves but
stability and transient response degrade. In the denominator
of Equation 24, the factor of 3 sets the minimum ramp size
that produces an optimal combination of good stability,
transient response, and thermal balance.
COMP Pin Ramp
the COMP pin due to the droop voltage and output voltage
ramps. This ramp amplitude adds to the internal ramp to
produce the following overall ramp signal at the PWM
input:
where C
resistance of the regulator.
Current Limit Setpoint
R
CC
R
D
DS
R
CLIM
The previous equation also shows the standby dissipation
The ramp resistor (R
where:
Another consideration in the selection of R
The internal ramp voltage magnitude can be calculated as
The size of the internal ramp can be increased or
In addition to the internal ramp, there is a ramp signal on
For this example, the overall ramp signal is 1.85 V.
To select the current limit setpoint, the resistor value for
is the internal ramp capacitor value.
is the internal ramp amplifier gain.
is the current balancing amplifier gain.
is the total low−side MOSFET ON−resistance;
times the VCC) of the driver.
V
V
must be determined. The current limit threshold for
R
R
X
V
+
+
is the total bulk capacitance, and R
R
R
RT
R
R
A
0.5
462 kW
+
R
+
+
R
R
3
3
1 *
(1 * D)
(1 * 0.061)
A
5
C
0.5
n f
D
R
R
A
5 pF
) is used to set the size of the internal
2 (1*n D)
R
SW
5.2 mW
V
R
f
R
360 nH
SW
DS
V
L
C
VID
280 kHz
X
1.150 V
R
C
O
5 pF
R
R
+ 462 kW
+ 0.83 V
in this example is
R
O
is the size of
is the droop
(eq. 24)
(eq. 25)
(eq. 26)
http://onsemi.com
31
the ADP3208D is set with R
the following equation:
where:
R
R
I
operation, the equation above is used to set the current limit.
When the ADP3208D switches from 2−phase to 1−phase
operation by PSI or DPRSLP signal, the current is
single−phase is one half of the current limit in 2−phase.
operation, the equation above is used to set the current limit.
Output Current Monitor
pin sources a current proportional to the total inductor
current. A resistor, R
gain of the output current monitor. A 0.1 mF is placed in
parallel with R
high frequency load transients. Since the IMON pin is
connected directly to the CPU, it is clamped to prevent it
from going above 1.15V.
gain of 10. R
R
from IMON pin to FBRTN.
R
R
I
scale.
Feedback Loop Compensation Design
possible response of the regulator’s output to a load change.
The basis for determining the optimum compensation is to
make the regulator and output decoupling appear as an output
impedance that is entirely resistive over the widest possible
frequency range, including dc, and that is equal to the droop
resistance (R
output voltage droops in proportion with the load current at
any load current slew rate, ensuring the optimal position and
allowing the minimization of the output decoupling.
ADP3208D, it is necessary to set the feedback compensation
so that the converter’s output impedance works in parallel
with the output decoupling. In addition, it is necessary to
compensate for the several poles and zeros created by the
output inductor and decoupling capacitors (output filter).
LIM
FS
LIM
O
MON
LIM
O
When the ADP3208D is configured for 2−phase
When the ADP3208D is configured for 1−phase
The ADP3208D has output current monitor. The IMON
The IMON pin current is equal to the R
where:
Optimized compensation of the ADP3208D allows the best
With the multi−mode feedback structure of the
is the output load line.
is the output load line resistance.
is the output current when the voltage on IMON is at full
is the current limit set point.
is the current limit resistor.
is the current limit resistor.
is the current monitor resistor. R
R
MON
MON
O
). With the resistive output impedance, the
MON
+
can be found using the following equation:
10
1.15 V
to filter the inductor current ripple and
MON
R
LIM
R
, from IMON to FBRTN sets the
O
CLIM
+
R
LIM
I
I
LIM
FS
. R
60 mA
CLIM
R
O
MON
can be found using
LIM
times a fixed
is connected
(eq. 27)
(eq. 28)