ADP3208DJCPZ-RL ON Semiconductor, ADP3208DJCPZ-RL Datasheet - Page 19

• Manufacturer Part Number: ADP3208DJCPZ-RL
• Description: IC CTLR BUCK 7BIT 2PHASE 48LFCSP
• Manufacturer: ON Semiconductor

Specifications of ADP3208DJCPZ-RL

• Applications: Controller, Power Supplies for Next-Generation Intel Processors
• Voltage - Input: 3.3 ~ 22 V
• Number Of Outputs: 1
• Voltage - Output: 0.01 ~ 1.5 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Output Voltage: 10 mV
• Output Current: 40 A
• Input Voltage: 19 V
• Supply Current: 6 mA
• Switching Frequency: 300 KHz
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 10 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

is set via the 7−bit VID DAC. The VID codes are listed in the
VID Code table. The noninverting input voltage is offset by
the droop voltage as a function of current, commonly known
as active voltage positioning. The output of the error
amplifier is the COMP pin, which sets the termination
voltage of the internal PWM ramps.
location using R
output voltage at the remote sensing point. The main loop
compensation is incorporated in the feedback network
connected between the FB and COMP pins.
Power−Good Monitoring
via the CSREF pin. The PWRGD pin is an open−drain
output that can be pulled up through an external resistor to
a voltage rail, not necessarily the same VCC voltage rail that
is running the controller. A logic high level indicates that the
output voltage is within the voltage limits defined by a range
around the VID voltage setting. PWRGD goes low when the
output voltage is outside of this range.
range is defined to be 300 mV less than and 200 mV greater
than the actual VID DAC output voltage. For any DAC
voltage less than 300 mV, only the upper limit of the
PWRGD range is monitored. To prevent a false alarm, the
power−good circuit is masked during various system
transitions, including a VID change and entrance into or exit
out of deeper sleep. The duration of the PWRGD mask is set
to approximately 130 ms by an internal timer. If the voltage
drop is greater than 200 mV during deeper sleep entry or
slow deeper sleep exit, the duration of PWRGD masking is
extended by the internal logic circuit.
Powerup Sequence and Soft−Start
internally. The powerup sequence, including the soft−start is
illustrated in Figure 29.
The core voltage ramps up linearly to the boot voltage. The
ADP3208D regulates at the boot voltage for 100 ms. After
the boot time is completed, CLKEN is asserted low. After
CLKEN is asserted low for 9ms, PWRGD is asserted high.
connecting the CSREF to GND. The MOSFET on the
CSREF pin has a resistance of approximately 100W. When
VCC ramps above the upper UVLO threshold and EN is
asserted high, the ADP3208D enables internal bias and
starts a reset cycle that lasts about 50 ms to 60 ms. Next, when
initial reset is over, the chip detects the number of phases set
by the user, and gives a go signal to start soft−start. The
ADP3208D reads the VID codes provided by the CPU on
VID0 to VID6 input pins after CLKEN is asserted low. The
PWRGD signal is asserted after a t
about 9 ms, as specified by IMVP−6+. The power−good
delay is programmed internally.
At the negative input, the FB pin is tied to the output sense
The power−good comparator monitors the output voltage
Following the IMVP−6+ specification, the PWRGD
The power−on ramp−up time of the output voltage is set
After EN is asserted high, the soft−start sequence starts.
In VCC UVLO or in shutdown, a small MOSFET turns on
B
, a resistor for sensing and controlling the
CPU_PWRGD
delay of
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threshold, both the SS capacitor and the PGDELAY
capacitor are reset to ground to prepare the chip for a
subsequent soft−start cycle.
Soft Transient
change but ignores new code for a minimum of 400 ns. This
delay is required to prevent the device from reacting to
digital signal skew while the 7−bit VID input code is in
transition. Additionally, the VID change triggers a PWRGD
masking timer to prevent a PWRGD failure. Each VID
change resets and retriggers the internal PWRGD masking
timer.
reduce inrush current during VID transitions. Reducing the
inrush current helps decrease the acoustic noise generated
by the MLCC input capacitors and inductors.
a new VID code is detected, the ADP3208D steps
sequentially through each VID voltage to the final VID
voltage. There is a PWRGD masking time of 100ms after the
last VID code is changed internally. Table 2 lists the soft
transient slew rate.
Current Limit
current sense amplifier to a programmable current limit
setpoint to provide current limiting function. The current
limit set point is set with a resistor connected from I
to CSCOMP pin. This is the R
Table 2. Soft Transient Slew Rate
1. DNC = Do Not Care.
Entrance to Deeper Sleep
Fast Exit from Deeper Sleep
Slow Exit from Deeper Sleep
Transient from V
If EN is taken low or VCC drops below the VCC UVLO
When a VID input changes, the ADP3208D detects the
The ADP3208D provides a soft transient function to
The soft transient feature is implemented internally. When
The ADP3208D compares the differential output of a
V
PWRGD
Figure 29. Powerup Sequence of ADP3208D
CORE
VID Transient
VCC
BOOT
EN
to VID
t
BOOT
CLKEN
t
DPRSLP
lim
CPU _PWRGD
HIGH
HIGH
DNC
LOW
resistor. During normal
1
−3.125mV/ms
+3.125mV/ms
±3.125mV/ms
+12.5mV/ms
Slew Rate
LIM
pin