ADP3208DJCPZ-RL ON Semiconductor, ADP3208DJCPZ-RL Datasheet - Page 29

• Manufacturer Part Number: ADP3208DJCPZ-RL
• Description: IC CTLR BUCK 7BIT 2PHASE 48LFCSP
• Manufacturer: ON Semiconductor

Specifications of ADP3208DJCPZ-RL

• Applications: Controller, Power Supplies for Next-Generation Intel Processors
• Voltage - Input: 3.3 ~ 22 V
• Number Of Outputs: 1
• Voltage - Output: 0.01 ~ 1.5 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Output Voltage: 10 mV
• Output Current: 40 A
• Input Voltage: 19 V
• Supply Current: 6 mA
• Switching Frequency: 300 KHz
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 10 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

in Step 1, an available 0603−size thermistor with a value
close to R
which has resistance values of A = 0.3359 and B = 0.0771.
Using the equations in Step 4, r
and r
thermistor of 220 kW would be a reasonable selection,
making k equal to 0.913. Finally, R
to be 72.1 kW and 166 kW. Choosing the closest 1% resistor
for R
73.3 kW is used for R
C
platforms is typically recommended by Intel. For systems
containing both bulk and ceramic capacitors, however, the
following guidelines can be a helpful supplement.
ceramic capacitance (C
type of capacitors used. Keep in mind that the best location
to place ceramic capacitors is inside the socket; however, the
physical limit is twenty 0805−size pieces inside the socket.
Additional ceramic capacitors can be placed along the outer
edge of the socket. A combined ceramic capacitor value of
200 mF to 300 mF is recommended and is usually composed
of multiple 10 mF or 22 mF capacitors.
within its limits. The upper limit is dependent on the VID
OTF output voltage stepping (voltage step, V
with error of V
critical capacitance for load release at a given maximum load
step, DI
r
r
CS2
CS1
OUT
r
For example, if a thermistor value of 100 kW is selected
The required output decoupling for processors and
Select the number of ceramics and determine the total
Ensure that the total amount of bulk capacitance (C
TH
4. Compute the relative values for r
5. Calculate R
6. Calculate values for R
(A * B)
CS2
+
+
+
TH
Selection
by using the following equations:
thermistor of the closest value available. In
addition, compute a scaling factor k based on the
ratio of the actual thermistor value used relative to
the computed one:
following equations:
O
1*r
1*r
. The current version of the IMVP−6+ specification
R
R
yields 165 kW. To correct for this approximation,
is 1.094. Solving for r
A
CS
1
CS1
CS2
1
CS2
CS2
(1 * A)
is the Vishay NTHS0603N04 NTC thermistor,
1
(1 * B)
*
+ R
+ R
*
r
ERR
1
r
r
k +
CS1
1
1
CS
CS
*r
); the lower limit is based on meeting the
TH
r
2
1
CS2
R
CS1
* A
= r
TH(CALCULATED)
Z
r
R
k
((1 * k) ) (k
1
). This is based on the number and
.
TH
TH(ACTUAL)
* B
r
(1 * B)
× R
CS1
CS1
CS1
CS
(1 * A)
TH
and R
, and then select a
CS1
is 0.359, r
yields 241 kW, so a
r
r
2
CS2
and R
CS2
) B
CS1
r
))
2
by using the
, r
* (A * B)
CS2
V
CS2
CS2
, in time, t
(1 * A)
, and r
are found
is 0.729,
(eq. 12)
(eq. 13)
(eq. 14)
http://onsemi.com
X
) is
TH
r
V
1
,
29
allows a maximum V
more than the VID voltage for a step−off load current.
transient response, the ESR of the bulk capacitor bank (R
should be less than two times the droop resistance, R
C
the VID OTF and/or the deeper sleep exit specifications and
may require less inductance or more phases. In addition, the
switching frequency may have to be increased to maintain
the output ripple.
capacitors (C
change is when the device exits deeper sleep, during which
the V
10 mV. If k = 3.1, solving for the bulk capacitance yields:
ESR of 7 mW each yields C
enough to limit the high frequency ringing during a load
change. This is tested using:
where:
Q is limited to the square root of 2 to ensure a critically
damped system.
C
C
X(MIN)
C
C
To meet the conditions of these expressions and the
For example, if 30 pieces of 10 mF, 0805−size MLC
Using six 330 mF Panasonic SP capacitors with a typical
Ensure that the ESL of the bulk capacitors (L
X(MAX)
x(MIN)
X(MIN)
X(MAX)
L
L
where:
X
X
CORE
v C
v 300 mF
w
is greater than C
w
v
v
1 )
Z
change is 220 mV in 22 ms with a setting error of
n
2
n
k + −1n
2
Z
R
= 300 mF) are used, the fastest VID voltage
k
22 ms
3.1
O
1 ) t
2
R
L
2.1 mW )
2
(2.1 mW)
2
O
330 nH
R
CORE
)
330 nH @ 27.9 A
V
Q
L
O
v
(2.1 mW)
V
ERR
1.4375 V
V
V
2
2
OSMAX
V
V
X(MAX)
VID
220 mV
DI
v
DI
2
overshoot (V
O
10 mV
27.9 A
X
V
O
220 mV
V
VID
= 1.98 mF and R
2 + 2 nH
v
n
2
, the system does not meet
2
1.4375 V
490 nH
k
V
1.4375 V
L
VID
3.1
R
* C
OSMAX
* 300 mF + 21 mF
O
2
z
2.1 mW
* 300 mF
* 1 * C
X
) of 10 mV
= 1.2 mW.
X
+ 1.0 mF
(eq. 15)
(eq. 16)
(eq. 17)
) is low
(eq. 18)
O
2
. If the
* 1
z
X
)