NCP1308DR2G ON Semiconductor, NCP1308DR2G Datasheet - Page 9

• Manufacturer Part Number: NCP1308DR2G
• Description: IC CTRLR PWM CM UVLO HV 8SOIC
• Manufacturer: ON Semiconductor

Specifications of NCP1308DR2G

• Pwm Type: Current Mode
• Number Of Outputs: 1
• Frequency - Max: 75kHz
• Voltage - Supply: 11 V ~ 20 V
• Buck: No
• Boost: No
• Flyback: Yes
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 125°C
• Package / Case: 8-SOIC (3.9mm Width)
• Frequency-max: 75kHz
• Output Current: 500 mA
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 20 V
• Fall Time: 20 ns
• Rise Time: 40 ns
• Synchronous Pin: No
• Topology: Flyback
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Duty Cycle: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: NCP1308DR2G; NCP1308DR2GOSTR

inserted between the current sense input and the sense
element. Every time the NCP1308 output driver goes low,
a 200 mA source forces a current to flow through the sense
pin (Figure 15): when the driver is high, the current source
is off and the current sense information is normally
processed. As soon as the driver goes low, the current
source delivers 200 mA and develops a ground-referenced
voltage across R
voltage, the current sense comparator stays in the high state
and the internal latch can be triggered by the next clock
cycle. Now, if because of a low load mode the feedback
voltage is below R
comparator permanently resets the latch and the next clock
cycle (given by the demagnetization detection) is ignored:
we are skipping cycles as shown in Figure 15. As soon as
the feedback voltage goes up again, there can be two
situations: the recurrent period is small and a new
demagnetization detection (next wave) signal triggers the
NCP1308. To the opposite, in low output power conditions,
no more ringing waves are present on the drain and the
toggling of the current sense comparator together with the
The skip level selection is done through a simple resistor
skip
together with the sense comparator initiates a new cycle when FB passes the skip level.
. If this voltage is below the feedback
Figure 16. When the primary natural ringing becomes too low, the internal Timeout
Timeout
Timeout
skip
Signal
Signal
Signal
Signal
Drain
Drain
level, then the current sense
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NCP1308
5 ms
9
Current Sense and Timeout Restart
internal 5 ms timeout initiates a new cycle start. In normal
operating conditions, e.g. when the drain oscillations are
generous, the demagnetization comparator can detect the
50 mV crossing and gives the “green light”, alone, to
re-active the power switch. However, when skip cycle
takes place (e.g. at low output power demands), the restart
event slides along the drain ringing waveforms (actually
the valley locations) which decays more or less quickly,
depending on the L
factor. The situation can thus quickly occur where the
ringing becomes too weak to be detected by the
demagnetization comparator: it then permanently stays
locked in a given position and can no longer deliver the
“green light” to the controller. To help in this situation, the
NCP1308 implements a 5 ms timeout generator: each time
the 50 mV crossing occurs, the timeout is reset. So, as long
as the ringing becomes too low, the timeout generator starts
to count and after 5 ms, it delivers its “green light”. If the
skip signal is already present then the controller restarts;
otherwise the logic waits for it to set the drive output high.
Figure 16 depicts these two different situations:
Dmg Restart
5 ms
primary
-C
parasitic
network damping