NCP1308DR2G ON Semiconductor, NCP1308DR2G Datasheet - Page 12

• Manufacturer Part Number: NCP1308DR2G
• Description: IC CTRLR PWM CM UVLO HV 8SOIC
• Manufacturer: ON Semiconductor

Specifications of NCP1308DR2G

• Pwm Type: Current Mode
• Number Of Outputs: 1
• Frequency - Max: 75kHz
• Voltage - Supply: 11 V ~ 20 V
• Buck: No
• Boost: No
• Flyback: Yes
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 125°C
• Package / Case: 8-SOIC (3.9mm Width)
• Frequency-max: 75kHz
• Output Current: 500 mA
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 20 V
• Fall Time: 20 ns
• Rise Time: 40 ns
• Synchronous Pin: No
• Topology: Flyback
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Duty Cycle: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: NCP1308DR2G; NCP1308DR2GOSTR

Soft-Start
soften the constraints occurring in the power supply during
startup. It is activated during the power on sequence. As
soon as V
increased from nearly zero up to the maximum clamping
level (e.g. 1.0 V). The soft-start is also activated during the
over current burst (OCP) sequence. Every restart attempt
is followed by a soft-start activation. Generally speaking,
the soft-start will be activated when V
from zero (fresh power-on sequence) or 5.3 V, the latchoff
voltage occurring during OCP.
Calculating the V
depends upon the V
V
depends on the startup sequence of your system, i.e. when
you first apply the power to the IC. The corresponding
transient fault duration due to the output capacitor charging
CC
The NCP1308 features an internal 1ms soft-start to
As the above section describes, the fall down sequence
line to go from 12 V to 10 V? The required time
FAULT FLAG
5.3 V
INTERNAL
12 V
10 V
CC
DRV
V
STARTUP PHASE
CC
reaches VCC
CC
CC
Capacitor
OCCURS HERE
level: how long does it take for the
REGULATION
OFF
, the peak current is gradually
CC
LATCHOFF
FAULT OCCURS HERE
PULSES
DRIVER
PHASE
ramps up either
http://onsemi.com
FAULT IS
RELAXED
Figure 22.
NCP1308
12
must be less than the time needed to discharge from 12 V
to 10 V, otherwise the supply will not properly start. The
test consists in either simulating or measuring in the lab
how much time the system takes to reach the regulation at
full load. Let's suppose that this time corresponds to 6ms.
Therefore a V
appropriated in order to not trigger the overload detection
circuitry. If the corresponding IC consumption, including
the MOSFET drive, establishes at 1.6 mA (e.g. with a
10 nC Qg), we can calculate the required capacitor using
the following formula:
for a wanted Δt of 10 ms, C equals 9 mF or 22 mF for a
standard value. When an overload condition occurs, the IC
blocks its internal circuitry and its consumption drops to
330 mA typical. This happens at V
stuck until V
Again, using the calculated 22 mF and 330 mA current
consumption, this latchoff phase lasts: 313 ms.
TIME
TIME
TIME
CC
CC
reaches 5.3 V: we are in latchoff phase.
If the fault is relaxed during the V
natural fall down sequence, the IC
automatically resumes.
If the fault still persists when V
reached VCC
cuts everything off until recovery.
fall time of 10 ms could be well
Dt + DV @ C
ON
i
, then the controller
CC
, with ΔV = 2 V. Then
= 10 V and it remains
CC
CC